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| general features ? single-package fully-integrated avr ? 8-bit microcontroller with lin transceiver, 5v regulator and watchdog ? very low current consumption in sleep mode ? 8 kbytes/16 kbytes flash memory for ap plication program (ata6602/ata6603) ? supply voltage up to 40v ? operating voltage: 5v to 18v ? temperature range: t case ?40c to +125c ? qfn48, 7 mm 7 mm package 1. description ata6602/ata6603 is a single-package dual-c hip circuit family for lin-bus slave node applications. it supports highly integrated solutions for in-vehicle lin networks. the lin-system-basis-chip (lin-sbc) consists of a lin transceiver, voltage regulator and window watchdog. the second chip is a microcontroller out of atmel ? 's series of avr 8-bit microcontrollers with advanced risc architecture. figure 1-1. application diagram mcu lin-sbc lin bus ata6602/ata6603 microcontroller with lin transceiver, 5v regulator and watchdog ata6602 ata6603 4921e?auto?09/09
2 4921e?auto?09/09 ata6602/ata6603 2. pin configuration figure 2-1. pinning qfn48, 7 mm 7 mm pc2 pc3 pc4 pc5 pc6 pd0 pd1 pd2 pd3 pd4 gnd vcc pb0 pd7 pd6 pd5 wake ntrig ptrig en vs vdd pvdd temp pc1 pc0 adc7 gnd aref adc6 avcc pb5 pb4 pb3 pb2 pb1 gnd vcc pb6 pb7 gnd lin rxd txd nres wd_osc tm mode 48 47 46 45 44 43 42 41 40 39 38 37 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 table 2-1. pin description pin symbol function 1 pc2 port c 2 i/o line (adc2/pcint10) 2 pc3 port c 3 i/o line (adc3/pcint11) 3 pc4 port c 4 i/o line (adc4/sda/pcint12) 4 pc5 port c 5 i/o line (adc5/scl/pcint13) 5 pc6 port c 6 i/o line (reset/pcint14) 6 pd0 port d 0 i/o line (rxd/pcint16) 7 pd1 port d 1 i/o line (txd/pcint17) 8 pd2 port d 2 i/o line (int0/pcint18) 9 pd3 port d 3 i/o line (int1/oc2b/pcint19) 10 pd4 port d 4 i/o line (t0/xck/pcint20) 11 gnd ground 12 vcc microcontroller supply voltage 13 gnd ground 14 vcc microcontroller supply voltage 15 pb6 port b 6 i/o line (tosc1/xtal1/pcint6) 16 pb7 port b 7 i/o line (tosc2/xtal2/pcint7) 17 gnd ground 18 lin lin bus connection 3 4921e?auto?09/09 ata6602/ata6603 19 rxd lin bus receiver output 20 txd lin bus transmitter input 21 nres watchdog and undervoltage reset output 22 wd_osc watchdog oscillator timing-resistor connection 23 tm tie to ground ? for factory use only 24 mode tie to ground ? for factory use only 25 temp system-basis-chip temperature monitor output 26 pvdd 5v voltage regulator sense input 27 vdd 5v voltage regulator output 28 vs battery connection 29 en lin-transceiver enable input 30 ptrig watchdog trigger input (positive edge) 31 ntrig watchdog trigger input (negative edge) 32 wake system-basis-chip external wake-up input 33 pd5 port d 5 i/o line (t1/oc0b/pcint21) 34 pd6 port d 6 i/o line (ain0/oc0a/pcint22) 35 pd7 port d 7 i/o line (ain1/pcint23) 36 pb0 port b 0 i/o line (icp1/clko/pcint0) 37 pb1 port b 1 i/o line (oc1a/pcint1) 38 pb2 port b 2 i/o line (oc1b/ss/pcint2) 39 pb3 port b 3 i/o line (mosi/oc2a/pcint3) 40 pb4 port b 4 i/o line (miso/pcint4) 41 pb5 port b 5 i/o line (sck/pcint5) 42 avcc microcontroller adc-unit supply voltage 43 adc6 adc input channel 6 44 aref analog reference voltage input 45 gnd ground 46 adc7 adc input channel 7 47 pc0 port c 0 i/o line (adc0/pcint8) 48 pc1 port c 1 i/o line (adc1/pcint9) backside heat slug is connected to gnd table 2-1. pin description (continued) pin symbol function 4 4921e?auto?09/09 ata6602/ata6603 3. lin system-basis-chip block 3.1 features ? supply voltage up to 40v ? operating voltage v s = 5v to 18v ? slew rate control according to lin specification 2.0 ? supply current during sleep mode typically 10 a ? supply current in silent mode typically 40 a ? linear low-drop voltage regulator: ? normal mode: v dd = 5v 2%/50 ma ? silent mode: v dd = 5v 7%/50 ma ? sleep mode: v dd is switched off ? v dd undervoltage detection (10 ms reset time) and watchdog reset logically combined at output nres ? possibility of boosting the voltage regulator with an external npn transistor ? lin physical layer accordin g to lin specification 2.0 ? wake-up capability via lin bus or wake pin ? wake-up recognition ? txd time-out timer ? debug mode watchdog is switched off ? 60v load dump protection at lin pin ? bus pin is overtemperature and short circuit protected versus gnd and battery ? adjustable watchdog time via external resistor ? positive and negative trigger input for watchdog ? 5v cmos compatible i/o pins to mcu ? analog temperature monitor output ? high emc and esd level 3.2 description the lin-sbc is a fully integrated lin transceiver, complying with the lin specification, and with a low-drop voltage regulator for 5v/50 ma output and a window watchdog adjustable via an external resistor. the voltage regulator is able to source 50 ma at v s = 18v even at an ambient temperature of 105c. the output current of the regulator can be boosted by using an external npn transistor. this combination makes it po ssible to develop simple, but powerful and cheap, slave nodes in lin bus systems. lin-sbc is designed to handle the low speed data communica- tion in vehicles, for example, in convenience elec tronics. improved slope control at the lin driver ensures secure data communication up to 20 kbaud. the bus output is capable of withstanding 60v. sleep mode and silent mode guarantee a very low current consumption. 5 4921e?auto?09/09 ata6602/ata6603 figure 3-1. block diagram v dd v dd v s adjustable watchdog oscillator short circuit and overtemperature protection txd time-out timer debounce time internal testing unit control unit slew rate control wake-up bus timer standby mode undervoltage reset normal mode 5v 2%/50 ma silent mode 5v 7%/50 ma filter watchdog out rxd gnd gnd ntrig ptrig tm mode temp en txd wake receiver v dd v dd normal mode lin wd_osc nres pvdd vdd vs 6 4921e?auto?09/09 ata6602/ata6603 3.3 functional description 3.3.1 supply pin (vs) the lin operating voltage is v s = 5v to 18v. after switching on vs, the ic starts with the pre-normal mode and the voltage regulator is switched on (that is, 5v/50 ma output capability). the supply current in sleep mode is typically 10 a, and 40 a in silent mode. 3.3.2 ground pin (gnd) the ic is neutral on the lin pin in case of gnd disconnection; it can handle a ground shift up to 3v for supply voltage at the vs pin above 9v. 3.3.3 undervoltage reset output (nres) this push-pull output is supplied from the v cc voltage. if the v cc voltage falls below the under- voltage detection threshold of v thun , nres switches to low after t res_f ( figure 3-8 on page 15 ) except the ic is switched into sleep mode. even if v cc = 0v the nres stays low, because it is internally driven from the v s voltage. if v s voltage ramps down, nres stays until v s < 1.5v and then becomes highly resistant. the implemented undervoltage delay keeps nres low for t reset =10ms after v cc reaches its normal value. 3.3.4 voltage regulator output pin (vdd) the internal 5v voltage regulator is capable of driving loads with up to 50 ma of current con- sumption; it is able to supply the microcontroller and other ics on the pcb. it is protected against overloads by means of current limitation and overtemperature shutdown. furthermore, the output voltage is monitored and will cause a reset signal at the nres output pin if the output voltage drops below a defined threshold v thun . to boost up the maximum load current, an exter- nal npn transistor may be used with its base connected to the vdd pin and its emitter connected to pvdd. 3.3.5 voltage regulator sense pin (pvdd) this is the sense input pin of the 5v voltage regulator. for normal applications (that is, when only using the internal output transistor), this pin is connected to the vdd pin. if an external boosting transistor is used, the pvdd pin must be c onnected to the output of this transistor, its emitter terminal. 3.3.6 bus pin (lin) a low side driver with internal current limi tation and thermal shutdown, and an internal pull-up resistor in compliance with lin specification 2.0 is implemented. this is a self-adapting current limitation; that is, during current limitation, as the chip temperature increases, the current decreases. the allowed voltage range is between ?40v and +60v. reverse currents from the lin bus to vs are suppressed, even in case of ground shifts or battery disconnection. lin receiver thresholds are compatible to the lin protocol specification. the fall time from recessive bus state to dominant, and the rise time from dominant bus state to recessive are slope controlled. 3.3.7 input/output pin (txd) this pin is the microcontroller interface to control the state of the lin output. txd must be pulled to ground in order to have the lin bus low. if txd is high, the lin output transistor is turned off and the bus is in the recessive state, pulled up by the internal resistor. 7 4921e?auto?09/09 ata6602/ata6603 3.3.8 txd dominant time-out function the txd input has an internal pull-up resistor. an internal timer prevents the bus line from being driven permanently in the dominant state. if txd is forced to low longer than t dom >6ms, the lin bus driver is switched to the recessive stat e. to reset this dominant time-out mode, txd must be switched to high (> 10 s) before normal data transmission can be started. 3.3.9 output pin (rxd) this pin reports the state of the lin bus to the microcontroller. lin high (recessive state) is reported by a high level at rxd, lin low (dominant state) is reported by a low level at rxd. the output has an internal pull-up structure with typically 5 k to v dd . the ac characteristics can be defined with an external load capacitor of 20 pf. the output is short-circuit protected. in unpowered mode (that is, v s = 0v), rxd is switched off. 3.3.10 enable input pin (en) this pin controls the operation mode of the interf ace. if en is high, the interface is in normal mode, with transmission paths from txd to lin and from lin to rxd both being active. the v dd voltage regulator is operating with 5v 2%/50 ma output capability. if en is switched to lo w while txd is still high, the device is forced to silent mode. no data trans- mission is then possible and the current consumption is reduced to i vs =50a. the current capability of the v dd regulator is also 50 ma, but the v dd tolerance is between 4.65v and 5.35v. if en is switched to low while txd is low, the device is forced to sleep mode. no data transmis- sion is possible and the voltage regulator is switched off. 3.3.11 wake input pin (wake) this pin is a high voltage input used to wake the device up from sleep mode. it is usually con- nected to an external switch in the application to generate a local wake-up. a pull-up current source with typically 10 a is implemented. if you do not need a local wake-u p in your application, connec t pin wake directly to pin vs. 3.3.12 mode input pin for normal watchdog operation connect pin mode via an external resistor to gnd. for debug- ging your software you can connect pin mode to 5v and the watchdog is switched off. 3.3.13 tm input pin pin tm is used in final production measurement at atmel. in the application it is always con- nected to gnd. 8 4921e?auto?09/09 ata6602/ata6603 3.3.14 modes of operation figure 3-2. modes of operation 3.3.14.1 normal mode this is the normal transmitting and receiving mode. the voltage regulator is in normal mode and can source 50 ma. the undervoltage detection is activated. the watchdog needs a trigger signal from ptrig or ntrig to avoid resets at nres. 3.3.14.2 silent mode a falling edge at en while txd is high switches the ic into silent mode . the txd signal has to be logic high during the mode select window (see figure 3-3 on page 9 ). for en and txd either two independent outputs can be used, or two outputs from the same microcontroller port; in the second case, the mode change is only one command. in silent mode, the transmission path is disabled. supply current from v bat is typically i vssi = 40 a with no load at the vdd regulator. the overall supply current from v bat is the addition of 40 a plus the v dd regulator output current i vdds . pre-normal mode vcc: 5v/50 ma with undervoltage monitoring communication: off a b silent mode vcc: 5v 7%/50 ma with undervoltage monitoring communication: off en = 1 go to silent command en = 0 txd = 1 local wake-up event a: v s > 5v b: v s < 4v c: bus wake-up event d: nres switches to low e : wake-up from wake-up switch b en = 1 b c + d + e normal mode vcc: 5v 2%/50 ma with undervoltage monitoring communication: on unpowered mode v batt = 0 sleep mode vcc: switched off communication : off go to sleep command local wake-up event en = 0 txd = 0 en = 1 b c + e d 9 4921e?auto?09/09 ata6602/ata6603 in silent mode, the 5v regulator is in low tolerance mode (4.65v to 5.35v) and can source up to 50 ma. the internal slave termination between pin lin and pin vs is disabled to minimize the power dissipation in case pin lin is shorted to gnd. only a weak pu ll-up current (typically 10 a) between pin lin and pin vs is present. the silent mode voltage tolerance is sufficient to run the internal timers of the microcontroller. the undervoltage reset is now v ddths < 4.4v. if an undervoltage condition occurs, the nres is switched to low and the lin-sbc changes state to pre-normal mode. a falling edge at pin lin followe d by a dominant bus level mainta ined for a certain time period (t bus ) results in a remote wake-up request. the device switches from silent mode to pre-normal mode. the internal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at pin rxd to interrupt the microcontroller (see figure 3-4 on page 10 ). with en high, you can switch directly from silent mode to normal mode. figure 3-3. switch to silent mode delay time silent mode t d _sleep = maximum 15 s mode select window lin switches directly to recessive mode t d = 3.2 s lin vcc nres txd en silent mode 10 4921e?auto?09/09 ata6602/ata6603 figure 3-4. lin wake-up waveform diagram from silent mode 3.3.14.3 sleep mode the falling edge at en has to occure not more than t dommin = 6 ms after or 3.2 s before the fall- ing edge at txd in order to switch the ic into sleep mode. the txd signal has to stay logic low during the mode select window (see figure 3-5 on page 11 and section ?silent mode? on page 8 ). in sleep mode the transmission path is disabled. supply current from v bat is typically i vssleep =10a. the v dd regulator is switched off. nres and rxd are low. the internal slave termination between pin lin and pin vs is disabled to minimize the power dissipation in case pin lin is shorted to gnd. only a weak pull-up current (typically 10 a) between pin lin and pin vs is present. a falling edge at pin lin followe d by a dominant bus level mainta ined for a certain time period (t bus ) results in a remote wake-up request. the device switches from sleep mode to pre-normal mode. the vdd regulator is activated and the inte rnal lin slave termination resistor is switched on. the remote wake-up request is indicated by a low level at pin rxd to interrupt the microcon- troller (see figure 3-6 on page 12 ). regulator wake-up time if undervoltage, switch to pre-normal mode undervoltage detection active silent mode pre-normal mode normal mode low pre-normal mode normal mode en high high nres en vcc rxd lin bus bus wake-up filtering time t bus vlin < 0.4 v s node in silent mode high txd 11 4921e?auto?09/09 ata6602/ata6603 with en high you can switch directly from silent mode to normal mode. in the application where the lin-sbc supplies the microcontroller, wake-up from sleep mode is only possible via lin or pin wake. if the device is switched into sleep mode, v dd ramps down without generating an undervoltage reset at pin nres. figure 3-5. switch to sleep mode delay time sleep mode t d _sleep = maximum 15 s mode select window lin switches directly to recessive mode t d = 3.2 s lin vcc nres txd en sleep mode 12 4921e?auto?09/09 ata6602/ata6603 figure 3-6. lin wake-up waveform diagram from sleep mode 3.3.14.4 pre-normal mode at system power-up the device automatically switches to pre-normal mode. the voltage regula- tor is switched on v dd = 5v 2%/50 ma (see figure 3-8 on page 15 ). the nres output switches to low for t res = 10 ms and sends a reset to the microcontroller. lin communication is switched off and the watchdog is active. the lin-sbc stays in this mode until en is switched to high. if v battery (v s < 4v) is powered down during silent mode or sleep mode, the ic powers up into pre-normal mode. during this mode the txd pin is an output. 3.3.14.5 unpowered mode if you connect battery voltage to the application circuit, the voltage at the vs pin increases due to the block capacitor (see figure 3-8 on page 15 ). when v s becomes higher than the v s under- voltage threshold v s_th , the ic mode changes from unpowered mode to pre-normal mode. the v dd output voltage reaches its nominal value after t vdd . this time depends on the v dd capacitor and the load. the nres is low for the reset time delay t reset . during this time, no mode change is possible. 3.3.14.6 debug mode the watchdog is switched off with pin mode high (5v) and in normal operation if it is tied to gnd. regulator wake-up time off state on state low pre normal mode normal mode high en high node ln operation microcontroller start-up time delay reset time low or floating low or floating nres en vcc voltage regulator rxd lin bus bus wake-up filtering time t bus 13 4921e?auto?09/09 ata6602/ata6603 3.3.15 wake-up scenarios from silent to sleep mode 3.3.15.1 remote wake-up via dominant bus state a falling edge at pin lin followe d by a dominant bus level mainta ined for a certain time period (t bus ) results in a remote wake-up request. the device switches to pr e-normal mode. the v dd voltage regulator is activated, and the internal slave termination resistor is switched on. the remote wake-up request is indicated by a low level at pin rxd to generate an interrupt in the microcontroller and a high level at pin txd. the watchdog needs a trigger signal from ptrig or ntrig within the lead time t d to avoid resets at nres (see figure 3-4 on page 10 ). 3.3.15.2 local wake-up via pin wake a falling edge at pin wake followed by a low level maintained for a certain time period (t wake ) results in a local wake-up reques t. the extra long wake-up time (t wake ) ensures that no tran- sients as defined in iso7637 create a wake-up. the device switches to pre-normal mode. the internal slave termination resistor is switched on. the local wake-up request is indicated by a low level at pin rxd to generate an interrupt in the microcontroller and a low level at pin txd. the watchdog needs a trigger signal from ptrig or ntrig within the lead time t d to avoid resets at nres. 3.3.15.3 wake-up source recognition the device can distinguis h between a local wake-up request (pin wake) and a remote wake-up request (dominant lin bus state). the wake-up source can be read on pin txd in pre-normal mode. a high level indicates a remote wake-up re quest and a low level indicates a local wake-up request. the wake-up request flag (signalled on pin rxd) as well as the wake-up source flag (signalled on pin txd) are reset immediately, if the microcontroller sets pin en to high (see fig- ure 3-3 on page 9 and figure 3-4 on page 10 ). if the lin-sbc is in sleep mode or silent mode and the voltage at the lin bus falls to a value lower than vlinl < vs ? 3.3v (see ?electrica l characteristics? on page 22, numbers 9.5 and 9.6) but remains higher than 0.6 vs, a local wake-up is in dicated after the time t wake by a low level at the pins rxd and txd (see figure 3-7 on page 14 ). table 3-1. table of modes mode of operation transceiver v dd wd_osc temp rxd lin pre-normal off 5v 2.5v 2v 5v recessive normal on 5v 2.5v 2v 5v recessive silent off 5v 0v 0v 5v recessive sleep off 0v 0v 0v 0v recessive 14 4921e?auto?09/09 ata6602/ata6603 figure 3-7. wake up source recognition 3.3.16 fail-safe features ? during a short circuit at lin, the output limits the output current to i bus_lim . due to the power dissipation, the chip temperature exceeds t linoff and the lin output is switched off. the chip cools down and after a hysteresis of t hys , switches the output on again. during lin overtemperature switch-off, the v dd regulator works independently. ? the reverse current at pin lin is very low (< 3 a) during loss of v bat or gnd. this is optimal behavior for bus systems where some slave modes are supplied from battery or ignition. ? during a short circuit at v dd , the output limits the output current to i vddn . because of undervoltage, nres switches to low and sends a reset to the microcontroller. the ic switches into pre-normal mode. if the chip temperature exceeds the value t vddoff , the v dd output switches off. the chip cools down and after a hysteresis of t hys , switches the output on again. because of pre-normal mode, the v dd voltage will switch on again although en is switched off from the microcontroller. the microcontroller can start its normal operation. ? pin en provides a pull-down resistor to force the transceiver into recessive mode if en is disconnected. ? pin rxd is connected with 5 k to v cc , if v batt is disconnected v cc is at gnd level ? pin txd provides a pull-up resistor to force the transceiver into recessive mode if txd is disconnected. regulator wake-up time if undervoltage, switch to pre-normal mode undervoltage detection active silent mode pre-normal mode normal mode low pre-normal mode normal mode en high high nres en vcc rxd lin bus wake-up filtering time t wake vlin < v s - 1v and vlin > 0.6 v s node in silent mode high txd low 15 4921e?auto?09/09 ata6602/ata6603 ? if the wd_osc pin has a short circuit to gnd or the resistor is disconnected, the watchdog oscillator runs with a high frequency and guarantee s a reset. in order to activate this feature in any condition it is recommended to enter the silent mode (via the normal mode) directly after power up. ? the wd_osc pin is a constant voltage regulator which supplies 2.5v for the external resistor rosc to adjust the watchdog timing. this output is short circuit protected. a short circuit to gnd causes a reset a pin nres after typically 4 ms. an open circuit causes a reset at pin nres after typically 7 ms. 3.3.17 voltage regulator the voltage regulator needs an external capacitor for compensation and to smooth the distur- bances from the microcontroller. it is recommend to use an tantalum capacitor with c > 1.8 f and a caramic capacitor with c = 100 nf. the values of these capacitors can be varied by the customer, depending on the application. during mode change from silent to normal mode, the voltage regulator ramps up to 6v for only a few microseconds before it drops back to 5v. this behavior depends on the value of the load capacitor. with 4.7 f, the overshoot voltage has its greatest value. this voltage decreases with higher or lower load capacitors. the main power dissipation of the ic is created from the v dd output current i vdd , which is needed for the application. in figure 3-9 on page 16 you see the safe operating range of the lin-sbc. figure 3-8. vdd voltage regulator: ramp up and undervoltage nres 5v vdd vs t t t 5v v thun t res_f t res t vcc 3v 5.5v 12v 16 4921e?auto?09/09 ata6602/ata6603 figure 3-9. power dissipation: safe operating area versus v dd output current and supply voltage v s at different ambient temperatures t case with r thja = 35 k/w for programming purposes at the microcontroller it is potentially necessary to supply the vcc output via an external supply while the vs pin of the system basis chip is disconnected. this behavior is no problem for the system basis chip. 3.3.18 watchdog the watchdog anticipates a trigger signal from the microcontroller at the ntrig (negative edge) or the ptrig (positive edge) input within a period time window of t wd . the trigger signal must exceed a minimum time t trigmin > 3 s. if a triggering signal is not received, a reset signal will be generated at output nres. the timi ng basis of the watchdog is pr ovided by the internal oscilla- tor, of which the time period t osc is adjustable via the external resistor r wd_osc (10 k to 120 k ). in silent or sleep mode, the watchdog is s witched off to reduce current consumption. minimum time for first watchdog pulse is required after the undervoltage reset at nres disap- pears and is defined as lead time t d . 3.3.18.1 typical timing sequence with r wd_osc = 51 k the trigger signal t wd is adjustable between 2.9 ms and 33 ms via the external resistor r wd_osc . for example, with an external resistor of r wd_oscsc =51k 1%, the typical parameters of the watchdog come out as follows: t osc = 12.5 s due to 51 k t d =3922 12.5 s = 49 ms t 1 =800 12.5 s = 10 ms t 2 =840 12.5 s = 10.5 ms t nres =157 12.5 s = 1.96 ms after every reset the watchdog always starts with the lead time. 0 5 10 15 20 25 30 35 40 45 50 55 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 v s (v) i vdd (ma) 125?c 105?c 17 4921e?auto?09/09 ata6602/ata6603 after ramping up the battery voltage v s or wake up from sleep mode, the 5v regulator is switched on. the reset output nres stays low for the time t reset (typically 10 ms), then it switches to high and the watchdog waits for t he watchdog sequence from the microcontroller. this lead time t d follows after the reset and is t d = 49 ms. after wake up from silent mode the rxd switches to low. the lead time t d follows the negative edge of this rxd signal. in this time, the first watchdog pulse from the microcontrolle r is required. if the trigger pulse ntrig (or ptrig, as the case may be) occurs during this time, the time t 1 starts immediately. if no trigger signal occurs during the time t d , a watchdog reset with t nres = 1.96 ms will reset the microcon- troller after t d = 49 ms. the times t 1 and t 2 have a fixed relationship with each other. a triggering signal from the microcontroller is anticipated within the time frame of t 2 = 10.5 ms. to avoid false triggering from glitches, the trigger pulse must be longer than t trigg > 3 s. this slope serves to restart the watchdog sequence. should the triggering signal fail in this open window t 2 , the nres output will be drawn to ground after t 2 . a triggering signal during the closed window t 1 causes nres to immediately switch low. figure 3-10. timing sequence with r wd_osc = 51 k 3.3.18.2 worst case calculation with r wo_osc = 51 k the internal oscillator has a tolerance of 20% . this means that t 1 and t 2 can also vary by 20%. the worst case calculation for the watchdog period t wd the microcontroller has to provide is calculated as follows. the ideal watchdog time t wd is between (t 1 maximum) and (t 1 minimum plus t 2 minimum). t 1,min = 0.8 t 1 = 8 ms, t 1,max = 1.2 t 1 = 12 ms t 2,min = 0.8 t 2 = 8.4 ms, t 2,max = 1.2 t 2 = 12.6 ms t wdmax = t 1min + t 2min = 8ms + 8.4ms = 16.4ms t wdmin = t 1max = 12 ms t wd = 14.2 ms 2.2 ms (15%) t nres = 1.9 m s undervoltage reset watchdog reset t reset = 10 ms t 1 = 10 ms t trigg > 3 s t 2 = 10.5 ms t 2 t 1 t wd t d = 49 ms v cc = 5v ptrig ntrig nres 18 4921e?auto?09/09 ata6602/ata6603 a microcontroller with an oscillator tolerance of 15% is sufficient to supply the trigger inputs correctly within the time period of t wd = 14.2 ms (15%) in an application with r wd_osc = 51 k . 3.3.19 temperature monitor at pin temp in addition to the internal temperature monitoring of the voltage regulator, an additional sensor measures the junction temperature and provides a linearized voltage at the temp pin. together with the analog functions of the microcontroller (for example, the analog comparator and the analog-to-digital converter (adc)), this enables the application to detect overload conditions and to take corresponding measures in order to prevent damage. an external capacitor buffers the voltage due to the input current of the adc. the sensor itself is built out of three diodes which are supplied by an internal bias current in pre-normal mode and normal mode. the typical voltage at t = 27c is v temp = 2.2v with a typi- cal negative temperature coefficient of v tc,temp = ?5.05 mv/k. in silent and sleep mode the 20 a current source is switched off. figure 3-11. temperature monitor table 3-2. table of watchdog timings rwd_osc k oscillator period t osc /s lead time t d /ms closed window t 1 /ms open window t 2 /ms trigger period from microcontroller t wd /ms reset time t nres /ms 10 2.6 10.2 2.08 2.18 2.90 0.41 51 12.5 49.4 10 10.5 14.2 1.96 91 22.4 87.8 17.92 18.82 25.45 3.52 120 29 113.7 23.2 24.36 32.94 4.55 temp 20 a v dd 19 4921e?auto?09/09 ata6602/ata6603 note: 1. t case means the temperature of the heat slug (backside). it is mandatory that this backside temperature is 125 c in the application. 3.4 absolute maximum ratings stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions beyond t hose indicated in the operational sections of this specification is not implied. exposure to absolute maximum rati ng conditions for extended periods may affect device reliability . parameters symbol min typ. max. unit supply voltage v s v s ?0.3 +40 v pulse time 500 ms t = 25c output current i vcc 50 ma v s +40 v pulse time 2min t = 25c output current i vcc 50 ma v s 27 v wake dc and tr ansient voltage (with 33 k serial resistor) transient voltage due to iso7637 (coupling 1 nf) ?40 ?150 +40 +100 v logic pins (rxd, txd, en, nres, ptrig, ntrig, vdd, pvdd, wd_osc, temp) ?0.3 +6.5 v output current nres i nres ?2 +2 ma lin - dc voltage - transient voltage ?40 ?150 +60 +100 v v dd dc voltage ?0.3 6.5 v maximum heat slug temperature t case (1) ?40 +125 c junction temperature t j ?40 +150 c storage temperature t s ?55 +150 c operating ambient temperature t a ?40 +125 c thermal resistance junc tion to heat slug r thjc 10 k/w thermal resistance junction to ambient, where heat slug is soldered to pcb r thja 35 k/w thermal shutdown of v dd regulator 150 165 170 c thermal shutdown of lin output 150 165 170 c thermal shutdown hysteresis 10 c 20 4921e?auto?09/09 ata6602/ata6603 3.5 electrical characteristics 5v < v s < 18v, t case = ?40c to +125c no. parameters test conditions pin symbol min. typ. max. unit type* 1 vs pin 1.1 nominal dc voltage range 28 v s 518va 1.2 supply current in sleep mode sleep mode v lin >v bat ? 0.5v v bat < 14v (25c to 125c) 28 i vssleep 10 20 a a 1.3 supply current in silent mode bus recessive; v bat < 14v (25c to 125c) without load at vdd 28 i vssi 40 50 a a 1.4 supply current in normal mode bus recessive without load at vdd 28 i vsrec 4maa 1.5 supply current in normal mode bus dominant vdd load current 50 ma 28 i vsdom 55 ma a 1.6 vs undervoltage threshold 28 vs th 4.15 4.5 5 v a 1.7 vs undervoltage threshold hysteresis 28 vs th_hys 0.2 v c 2 rxd output pin 2.1 low-level input current normal mode; v lin =0v v rxd =0.4v 19 irxd 2 5 8 ma a 2.2 low-level output voltage i rxd = 1 ma 19 vrxdl 0.3 v a 2.3 internal 5 k resistor to vdd 19 rrxd 3 7 k a 3 txd pin 3.1 low-level voltage input 20 v txdl ?0.3 +1.5 v a 3.2 high-level voltage input 20 v txdh 3.5 vdd + 0.3v va 3.3 pull-up resistor v txd = 0v 20 r txd 125 250 600 k a 3.4 high-level leakage current v txd = 5v 20 i txd ?3 +3 a a 3.5 low-level output current at local wake-up pre-normal mode, vtxd = 0.4v to 5v 20 i txdwake 258maa 4en input pin 4.1 low-level voltage input 29 v enl ?0.3 +1.5 v a 4.2 high-level voltage input 29 v enh 3.5 vdd + 0.3v va 4.3 pull-down resistor v en = 5v 29 r en 125 250 600 k a 4.4 low-level input current v en = 0v 29 i en ?3 +3 a a *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 21 4921e?auto?09/09 ata6602/ata6603 5 nres output pin 5.1 high-level output voltage v s 5.5v; i nres = ?1 ma 21 v nresh 4.5 v a 5.2 low-level output voltage v s 5.5v; i nres = +1 ma, i nres = +250 a 21 v nresl 0.2 0.14 v v a a 5.3 low-level output low 10 k to vdd; v dd = 0.8v 21 v nresll 0.3 v a 5.4 undervoltage reset time v vs 5.5v c nres = 20 pf 21 t reset 713msa 5.5 reset debounce time for falling edge v vs 5.5v c nres =20pf 21 t res_f 3sa 6 voltage regulator vdd pin in normal and pre-normal mode 6.1 output voltage vdd 5.5v < v s < 18v (0 ma to 50 ma) 27 vdd nor 4.9 5.1 v a 6.2 output voltage vdd at low vs 3.3v < v s < 5.5v 27 vdd low v vs ? v d 5.1 v a 6.3 regulator drop voltage v s > 4.0v, i vdd = ?20 ma 27 v d1 250 mv a 6.4 regulator drop voltage v s > 4.0v, i vdd = ?50 ma 27 v d2 500 mv a 6.5 regulator drop voltage v s > 3.3v, i vdd = ?15 ma 27 v d3 200 mv a 6.6 output current v s > 3v 27 i vdd ?50 ma a 6.7 output current limitation v s > 0v 27 i vdds ?200 ?130 ma a 6.8 load capacity 1 < esr < 5 at 100 khz 27 c load 1.8 2.2 f d 6.9 vdd undervoltage threshold referred to vdd v s > 5.5v 27 v thunn 4.4 4.8 v a 6.10 hysteresis of undervoltage threshold referred to vdd v s > 5.5v 27 vhys thun 30 mv a 6.11 ramp up time v s > 5.5v to vdd > 4.9v c vdd = 4.7 f no load 27 t vdd 300 s a 7 voltage regulator vdd pin in silent mode 7.1 output voltage vdd 5.5v < v s < 18v (0 ma to 50 ma) 27 vdd nor 4.65 5.35 v a 7.2 output voltage vdd at low vs 3.3v < v s <5.5v 27 vdd low v vs ? v d 5.1 v a 7.3 regulator drop voltage v s >3.3v, i vdd =?15ma 27 v d 200 mv a 7.4 at vcc undervoltage threshold the state switches back to pre-normal mode referred to vcc v s > 5.5 27 v thuns 3.9 4.4 v a 7.5 hysteresis of undervoltage threshold referred to vcc v s > 5.5v 27 vhys thun 40 mv d 7.6 output current limitation v s > 0v 27 i vccs ?200 ?130 ma a 3.5 electrical characteristics (continued) 5v < v s < 18v, t case = ?40c to +125c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 22 4921e?auto?09/09 ata6602/ata6603 8 lin bus driver: bus load conditions: load1 (small): 1 nf, 1 k ; load2 (large): 10 nf, 500 ; rrxd = 5 k ; c rxd = 20 pf 10.5, 10.6 and 10.7 specify the timing parameters for proper operation at 20 kbps 8.1 driver recessive output voltage load1/load2 18 v busrec 0.9 v s v s va 8.2 driver dominant voltage v vs =7v r load =500 18 v _losup 1.2 v a 8.3 driver dominant voltage v vs =18v r load =500 18 v _hisup 2va 8.4 driver dominant voltage v busdom_drv_losup v vs = 7v r load = 1000 18 v _losup_1k 0.6 v a 8.5 driver dominant voltage v vs = 18v r load =1000 18 v _hisup_1k_ 0.8 v a 8.6 pull-up resistor to vs the serial diode is mandatory 18 r lin 20 30 60 k a 8.7 self-adapting current limitation v bus =v batt_max t j = 125c t j = 27c t j = ?40c 18 i bus_lim 52 100 120 110 170 230 ma ma ma a 8.8 input leakage current at the receiver including pull-up resistor as specified input leakage current driver off v bus =0v v battery =12v 18 i bus_pas_dom ?1 ma a 8.9 leakage current lin recessive driver off 8v < v battery <18v 8v < v bus < 18v v bus v batt 18 i bus_pas_rec 15 20 a a 8.10 leakage current when control unit disconnected from ground. loss of local ground must not affect communication in the residual network gnd device = v s v battery = 12v 0v < v bus < 18v 18 i bus_no_gnd ?10 0.5 10 a a 8.11 node has to sustain the current that can flow under this condition. bus must remain operational under this condition v battery disconnected v sup_device = gnd 0v < v bus < 18v 18 i bus 0.5 3 a a 9 lin bus receiver 9.1 center of receiver threshold v bus_cnt = (v th_dom + v th _ rec )/2 18 v bus_cnt 0.475 v s 0.5 v s 0.525 ? v s va 9.2 receiver dominant state v en = 5v 18 v busdom ?27 0.4 v s va 9.3 receiver recessive state v en = 5v 18 v busrec 0.6 v s 40 v a 9.4 receiver input hysteresis v hys = v th_rec ? v th_dom 18 v bushys 0.028 v s 0.1 v s 0.175 v s va 9.5 wake detection lin high-level input voltage 18 v linh v s ?1v v s + 0.3v v a 9.6 wake detection lin low-level input voltage initializes a wake-up signal 18 v linl ?27 v s ?3.3v v a 3.5 electrical characteristics (continued) 5v < v s < 18v, t case = ?40c to +125c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 23 4921e?auto?09/09 ata6602/ata6603 10 internal timers 10.1 dominant time for wake-up via lin bus v lin = 0v t bus 30 90 150 s a 10.2 time delay for mode change from pre-normal to normal mode via pin en v en = 5v t norm 51520sa 10.3 time delay for mode change from normal into sleep mode via pin en v en = 0v t sleep 2 7 15 s a 10.4 txd dominant time-out timer v txd = 0v t dom 61020msa 10.5 duty cycle 1 th rec(max) = 0.744 v s ; th dom(max) = 0.581 v s ; v s = 7.0v to 18v; t bit =50s d1 = t bus_rec(min) / (2 t bit ) d1 0.396 a 10.6 duty cycle 2 th rec(min) = 0.422 vs; th dom(min) = 0.284 vs; v s = 7.0v to 18v; t bit = 50 s d2 = t bus_rec(max) / (2 t bit ) d2 0.581 a 10.7 slope time falling and rising edge at lin slope time dominant and recessive edges t slope_fall t slope_rise 3.5 22.5 s a 10.8 time of low pulse for wake-up via pin wake v wake = 0v t wake 60 130 200 s a 11 internal receiver electrical ac parameters of the li n physical layer lin receiver, rxd load conditions (c rxd ): 20 pf 11.1 propagation delay of receiver (see figure 3-12 on page 25 ) t rec_pd = max (t rx _ pdr , t rx_pdf )19t rx_pd 6sa 11.2 symmetry of receiver propagation delay rising edge minus falling edge t rx_sym = t rx_pdr ? t rx_pdf 19 t rx_sym ?2 2 s a 12 watchdog input ptrig and ntrig 12.1 watchdog input high-level threshold 30, 31 v_h ptrig 3.5 v a 12.2 watchdog input low threshold 30, 31 v_l ptrig 1.5 v a 12.3 internal pull down ptrig internal pull up ntrig 30, 31 rpd ptrig rpu ntrig 250 600 k a 3.5 electrical characteristics (continued) 5v < v s < 18v, t case = ?40c to +125c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 24 4921e?auto?09/09 ata6602/ata6603 13 watchdog oscillator 13.1 voltage at wd_osc in normal mode i wd_osc = ?250 a 22 v wd_osc 2.3 2.5 2.7 v a 13.2 possible values of resistor r osc 10 120 k d 13.3 oscillator period r osc = 10 k t osc 2.1 2.6 3.1 s a 13.4 oscillator period r osc = 51 k t osc 10 12.5 15 s a 13.5 oscillator period r osc = 91 k t osc 17.9 22.4 26.8 s a 13.6 oscillator period r osc = 120 k t osc 23.2 29 34.8 s a 14 watchdog timing relative to t osc 14.1 watchdog lead time after reset t d 3922 cycles a 14.2 watchdog closed window t 1 800 cycles a 14.3 watchdog open window t 2 840 cycles a 14.4 watchdog reset time nres t nres 157 cycles a 15 temperature monitor at pin temp 15.1 voltage at temp in normal mode (t = ?40c) i temp = 3 a 25 v temp 2.35 2.7 v a 15.1 voltage at temp in normal mode (t = 27c) i temp = 3 a 25 v temp 2.0 2.35 v a 15.1 voltage at temp in normal mode (t = 125c) i temp = 3 a 25 v temp 1.4 1.9 v a 15.2 short current at temp vtemp = 0v 25 i temp ?30 ?15 a a 15.3 temperature gradient 25 v tc,temp 4.8 5.05 5.3 mv/k c 16 wake pin 16.1 high-level input voltage 32 v wakeh v s ? 1v v s + 0.3v v a 16.2 low-level input voltage initializes a wake-up signal 32 v wakel ?27 v s ? 3.3v v a 16.3 wake pull-up current v s < 27v, v wake = 0v 32 i wake ?30 ?10 a a 16.4 high-level leakage current v s = 27v; v wake = 27v 32 i wakel ?5 +5 a a 17 mode input pin 17.1 low-level voltage input v model ?0.3 +0.8v v a 17.2 high-level voltage input v modeh 2v s + 0.3v v a 17.3 high-level leakage current v mode = vcc or v mode = 0v i mode ?3 +3 a a 3.5 electrical characteristics (continued) 5v < v s < 18v, t case = ?40c to +125c no. parameters test conditions pin symbol min. typ. max. unit type* *) type means: a = 100% tested, b = 100% correlation tested, c = characterized on samples, d = design parameter 25 4921e?auto?09/09 ata6602/ata6603 figure 3-12. definition of bus timing parameters txd (input to transmitting node) vs (transceiver supply of transmitting node) rxd (output of receiving node1) rxd (output of receiving node2) lin bus signal thresholds of receiving node1 thresholds of receiving node2 t bus_rec(max) t rx_pdr(1) t rx_pdf(2) t rx_pdr(2) t rx_pdf(1) t bus_dom(min) t bus_dom(max) th rec(max) th dom(max) th rec(min) th dom(min) t bus_rec(min) t bit t bit t bit 26 4921e?auto?09/09 ata6602/ata6603 4. microcontroller block 4.1 features ? high performance, low power avr 8-bit microcontroller ? advanced risc architecture ? 131 powerful instructions - mo st single clock cycle execution ?32 8 general purpose working register ? fully static operation ? up to 16 mips throughput at 16 mhz ? on-chip 2-cycle multiplier ? non-volatile program and data memories ? 8/16 kbytes of in-system self-programmable flash (ata6602/ata6603) endurance: 75,000 write/erase cycles ? optional boot code section with independent lock bits in-system programming by on-chip boot program true read-while-write operation ? 512 bytes eeprom endurance: 100,000 write/erase cycles ? 1 kbyte internal sram ? programming lock for software security ? peripheral features ? two 8-bit timer/counters with se parate prescaler and compare mode ? one 16-bit timer/counter with separate prescaler, compare mode, and capture mode ? real time counter with separate oscillator ? six pwm channels ? 8-channel 10-bit adc ? programmable serial usart ? master/slave spi serial interface ? byte-oriented 2-wire serial interface ? programmable watchdog timer with separate on-chip oscillator ? on-chip analog comparator ? interrupt and wake-up on pin change ? special microcontroller features ? power-on reset and programm able brown-out detection ? internal calibrated oscillator ? external and internal interrupt sources ? five sleep modes: idle, adc noise reducti on, power-save, power-down, and standby ? i/o ? 23 programmable i/o lines ? operating voltage ? 2.7v to 5.5v ? speed grade ? 0 to 8 mhz at 2.7v to 5.5v, 0 to 16 mhz at 4.5v to 5.5v ? low power consumption ?active mode: ? 4 mhz, 3.0v: 1.8 ma ? power-down mode: ? 5 a at 3.0v 27 4921e?auto?09/09 ata6602/ata6603 4.2 overview the ata6602/ata6603 uses a low-power cmos 8-bit microcontroller based on the avr enhanced risc architecture. by executing powerful instructions in a single clock cycle, the ata6602/ata6603 achieves throughputs appr oaching 1 mips per mhz allowing the system designer to optimize power consum ption versus processing speed. 4.2.1 block diagram figure 4-1. block diagram watchdog timer watchdog oscillator oscillator circuits / clock generation eeprom avr cpu flash sram program logic debugwire power supervision por / bod and reset 8 bit t/c 0 16 bit t/c 1 a/d converter 8 bit t/c 2 analog compensation internal bandgap usart 0 spi twi port d (8) port b (8) port c (7) gnd vcc gnd aref avcc data b u s 2 6 reset xtal[1..2 ] adc[6..7] pc[0..6] pb[0..7] pd[0..7] 28 4921e?auto?09/09 ata6602/ata6603 the avr core combines a rich instruction set with 32 general purpose working registers. all the 32 registers are directly connected to the arithmetic logic unit (alu), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. the resulting architecture is more code efficient while achiev ing throughputs up to ten times faster than con- ventional cisc microcontrollers. the ata6602/ata6603 provides the following f eatures: 8k/16k bytes of in-system program- mable flash with read-while-write capabi lities, 512 bytes eeprom, 1 kbyte sram, 23 general purpose i/o lines, 32 general purpose working registers, three flexible timer/coun- ters with compare modes, internal and external interrupts, a serial programmable usart, a byte-oriented 2-wire serial interface, an spi serial port, a 6-channel 10-bit adc (8 channels in tqfp and qfn packages), a pr ogrammable watchdog timer with internal oscillator, and five software selectable power saving modes. the idle mode stops the cpu while allowing the sram, timer/counters, usart, 2-wire serial in terface, spi port, and interrupt system to con- tinue functioning. the power-do wn mode saves the register cont ents but freeze s the oscillator, disabling all other chip functions until the next interrupt or hardware reset. in power-save mode, the asynchronous timer continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. the adc noise reduction mode stops the cpu and all i/o mod- ules except asynchronous timer and adc, to mi nimize switching noise during adc conversions. in standby mode, the crys tal/resonator oscillator is running while the rest of the device is sleep- ing. this allows very fast start-up combined with low power consumption. the device is manufactured using atmel?s hi gh density non-volatile me mory technology. the on-chip isp flash allows the program memory to be reprogrammed in-system through an spi serial interface, by a conventional non-volatile memory programmer, or by an on-chip boot pro- gram running on the avr core. the boot program can use any interface to download the application program in the applic ation flash memory. software in the boot flash section will continue to run while the application flash se ction is updated, providing true read-while-write operation. by combining an 8-bit risc cpu with in-system self-programmable flash on a monolithic chip, the atmel ata6602/ata6603 uses a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. the ata6602/ata6603 avr is supported with a full suite of program and system development tools including: c compilers, macro assemblers, program debugger/simulators, in-circuit emu- lator, and evaluation kits. 4.2.2 automotive quality grade the ata6602 and ata6603 have been developed and manufactured according to the most stringent requirements of the international standard iso-ts-16949 grade 1. this data sheet con- tains limit values extracted from the results of extensive characterization (temperature and voltage). the quality and reliability of the ata6602 and ata66 03 have been verified during reg- ular product qualification as per aec-q100. 29 4921e?auto?09/09 ata6602/ata6603 4.2.3 comparison between ata6602/ata6603 the ata6602 and ata6603 differ only in memory sizes, boot loader support, and interrupt vec- tor sizes. table 4-1 summarizes the different memory and interrupt vector sizes for the two devices. ata6602 and ata6603 support a real read-whil e-write self-programming mechanism. there is a separate boot loader section, and the spm instruction can only execute from there. 4.2.4 pin descriptions 4.2.4.1 vcc digital supply voltage. 4.2.4.2 gnd ground. 4.2.4.3 port b (pb7:0) xt al1/xtal2/tosc1/tosc2 port b is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port b output buffers have symmetrical drive characteristics with both high sink and source capability. as inputs, port b pi ns that are externally pulled low will source current if the pull-up resistors are activated. the port b pins are tri-stated when a reset condition becomes active, even if the clock is not running. depending on the clock selection fuse settings, pb6 can be used as input to the inverting oscil- lator amplifier. depending on the clock selection fuse settings, pb7 can be used as input to the inverting oscil- lator amplifier. if the internal calibrated rc oscillator is used as chip clock source, pb7..6 is used as tosc2..1 input for the asynchronous timer/counter2 if the as2 bit in assr is set. the various special features of port b are elaborated in ?alternate functions of port b? on page 95 and ?system clock and clock options? on page 49 . table 4-1. memory size summary device flash eeprom ram int errupt vector size ata6602 8 kbytes 512 bytes 1 kbyte 1 instruction word/vector ata6603 16 kbytes 512 bytes 1 kb yte 2 instruction words/vector 30 4921e?auto?09/09 ata6602/ata6603 4.2.4.4 port c (pc5:0) port c is a 7-bit bi-directional i/o port with inte rnal pull-up resistors (selected for each bit). the pc5..0 output buffers have symmetrical drive char acteristics with both high sink and source capability. as inputs, port c pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port c pins are tri-stated when a reset condition becomes active, even if the clock is not running. 4.2.4.5 pc6/reset if the rstdisbl fuse is unprogrammed, pc6 is used as a reset input. a low level on this pin for longer than the minimum pulse length will generate a reset, even if the clock is not running. the minimum pulse length is given in table 4-3 on page 45 . shorter pulses are not guaranteed to generate a reset. the various special features of port c are elaborated in ?alternate functions of port c? on page 99 . 4.2.4.6 port d (pd7:0) port d is an 8-bit bi-directional i/o port with internal pull-up resistors (selected for each bit). the port d output buffers have symmetrical drive c haracteristics with bot h high sink and source capability. as inputs, port d pi ns that are externally pulled lo w will source current if the pull-up resistors are activated. the port d pins are tri-stated when a reset condition becomes active, even if the clock is not running. the various special features of port d are elaborated in ?alternate functions of port d? on page 102 . 4.2.4.7 av cc av cc is the supply voltage pin for the a/d converter, pc3:0, and adc7:6. i should be externally connected to v cc , even if the adc is not used. if the adc is used, it should be connected to v cc through a low-pass filter. note that pc6..4 use digital supply voltage, v cc . 4.2.4.8 aref aref is the analog reference pin for the a/d converter. 4.2.4.9 adc7:6 (tqfp and qfn package only) in the tqfp and qfn package, adc7:6 serve as analog inputs to the a/d converter. these pins are powered from the analog supply and serve as 10-bit adc channels. 31 4921e?auto?09/09 ata6602/ata6603 4.3 about code examples this documentation contains simple code examples that briefly show how to use various parts of the device. these code examples assume that the part specific header file is included before compilation. be aware that not all c compiler vendors include bit definitions in the header file and interrupt handling in c is compiler dependent. please confirm with the c compiler documen- tation for more details. 4.4 avr cpu core 4.4.1 introduction this section discusses the avr core architecture in general. the main function of the cpu core is to ensure correct program execution. the cpu must therefore be able to access memories, perform calculations, control peripherals, and handle interrupts. 4.4.2 architectural overview figure 4-2. block diagram of the avr architecture interrupt unit spi unit watchdog timer analog comparator i/o module 1 i/o module 2 i/o module n status and control 32 8 general purpose registers alu data sram eeprom i/o lines data bus 8-bit program counter flash program memory instruction register instruction decoder control lines direct addressing indirect addressing 32 4921e?auto?09/09 ata6602/ata6603 in order to maximize performance and parallelism, the avr uses a harvard architecture ? with separate memories and buses for program and data. instructions in the program memory are executed with a single level pipelining. while one instruction is being executed, the next instruc- tion is pre-fetched from the program memory. this concept enables instructions to be executed in every clock cycle. the program memory is in-system reprogrammable flash memory. the fast-access register file contains 32 8-bit general purpose working registers with a single clock cycle access time. this allows single-cycle ar ithmetic logic unit (alu ) operation. in a typ- ical alu operation, two operands are output from the register file, the operation is executed, and the result is stored back in the register file ? in one clock cycle. six of the 32 registers can be used as three 16-bit indirect address register pointers for data space addressing ? enabling efficient address calculations. one of the these address pointers can also be used as an address pointer for look up tables in flash program memory. these added function registers are the 16-bit x-, y-, and z-register, described later in this section. the alu supports arithmetic and logic operations between registers or between a constant and a register. single register operations can also be executed in the alu. after an arithmetic opera- tion, the status register is updated to reflect information about the result of the operation. program flow is provided by conditional and uncon ditional jump and call instructions, able to directly address the whole address space. most avr instructions have a single 16-bit word for- mat. every program memory address contains a 16- or 32-bit instruction. program flash memory space is divided in two sections, the boot program section and the application program section. both sections have dedicated lock bits for write and read/write protection. the spm instruction that writes into the application flash memory section must reside in the boot program section. during interrupts and subroutine calls, the return address program counter (pc) is stored on the stack. the stack is effectively allocated in the general data sram, and consequently the stack size is only limited by the total sram size an d the usage of the sram. all user programs must initialize the sp in the reset routine (before subroutines or interrupts are executed). the stack pointer (sp) is read/write accessible in the i/o space. the data sram can easily be accessed through the five different addressing modes supported in the avr architecture. the memory spaces in the avr architecture are all linear and regular memory maps. a flexible interrupt module has its control r egisters in the i/o space with an additional global interrupt enable bit in the status register. all interrupts have a separate interrupt vector in the interrupt vector table. the interrupts have priority in accordance with their interrupt vector posi- tion. the lower the interrupt vector address, the higher the priority. the i/o memory space contains 64 addresses for cpu peripheral functi ons as control regis- ters, spi, and other i/o functions. the i/o memory can be accessed directly, or as the data space locations following those of the register file, 0x20 - 0x5f. in addition, the ata6602/ata6603 has extended i/o space from 0x60 - 0xff in sram where only the st/sts/std and ld/lds/ldd instructions can be used. 33 4921e?auto?09/09 ata6602/ata6603 4.4.3 alu ? arithmetic logic unit the high-performance avr alu operates in dire ct connection with all the 32 general purpose working registers. within a single clock cycle, arithmetic operations between general purpose registers or between a register and an immediate are executed. the alu operations are divided into three main categories ? arithmetic, logical, and bit-functions. some implementations of the architecture also provide a powerful multiplier supporting both signed/unsigned multiplication and fractional format. see the ?instruction set? section for a detailed description. 4.4.4 status register the status register contains information about the result of the most recently executed arithme- tic instruction. this information can be used for altering program flow in order to perform conditional operations. note that the status register is updated after all alu operations, as specified in the instruction set reference. this will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. the status register is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. this must be handled by software. the avr status register ? sreg ? is defined as: ? bit 7 ? i: global interrupt enable the global interrupt enable bit must be set for the interrupts to be enabled. the individual interrupt enable control is then performed in separate control registers. if the global interrupt enable register is cleared, none of the interrupts are enabled independent of the individual interrupt enable settings. the i-bit is cleared by hardware after an interrupt has occurred, and is set by the reti instruction to enable subsequent interrupts. the i-bit can also be set and cleared by the application with the sei and cli instructions, as described in the instruc- tion set reference. ? bit 6 ? t: bit copy storage the bit copy instructions bld (bit load) and bst (bit store) use the t-bit as source or destination for the operated bit. a bit from a register in the register file can be copied into t by the bst instruction, and a bit in t can be copied into a bit in a register in the register file by the bld instruction. ? bit 5 ? h: half carry flag the half carry flag h indicates a half carry in some arithmet ic operations. half carry is useful in bcd arithmetic. see the ?instruction set description? for detailed information. ? bit 4 ? s: sign bit, s = n v the s-bit is always an exclusive or between the negative flag n and the two?s comple- ment overflow flag v. see the ?instruction set description? for detailed information. bit 76543210 i t h s v n z c sreg read/write r/wr/wr/wr/wr/wr/wr/wr/w initial value 00000000 34 4921e?auto?09/09 ata6602/ata6603 ? bit 3 ? v: two?s complement overflow flag the two?s complement overflow flag v supports two?s complement arithmetics. see the ?instruction set description? for detailed information. ? bit 2 ? n: negative flag the negative flag n indicates a negative result in an arithmetic or logic operation. see the ?instruction set description? for detailed information. ? bit 1 ? z: zero flag the zero flag z indicates a zero result in an arithmetic or logic operation. see the ?instruc- tion set description? for detailed information. ? bit 0 ? c: carry flag the carry flag c indicates a carry in an arithm etic or logic operation. see the ?instruction set description? for detailed information. 4.4.5 general purpose register file the register file is optimized for the avr enhanc ed risc instruction set. in order to achieve the required performance and flex ibility, the following in put/output schemes ar e supported by the register file: ? one 8-bit output operand and one 8-bit result input ? two 8-bit output operands and one 8-bit result input ? two 8-bit output operands and one 16-bit result input ? one 16-bit output operand and one 16-bit result input figure 4-3 shows the structure of the 32 general purpose working registers in the cpu. figure 4-3. avr cpu general purpose working registers general purpose working registers 7 0 address r0 0x00 r1 0x01 r2 0x02 ... r13 0x0d r14 0x0e r15 0x0f r16 0x10 r17 0x11 ... r26 0x1a x-register low byte r27 0x1b x-register high byte r28 0x1c y-register low byte r29 0x1d y-register high byte r30 0x1e z-register low byte r31 0x1f z-register high byte 35 4921e?auto?09/09 ata6602/ata6603 most of the instructions operating on the register file have direct access to all registers, and most of them are single cycle instructions. as shown in figure 4-3 on page 34 , each register is also assigned a data memory address, mapping them directly into the first 32 location s of the user data space. although not being physically implemented as sram locations, this memory organiza tion provides great flexibility in access of the registers, as the x-, y- and z-pointer registers can be set to index any register in the file. 4.4.5.1 the x-register, y-register, and z-register the registers r26..r31 have some added functions to their general purpose usage. these reg- isters are 16-bit address pointers for indirect addressing of the data space. the three indirect address registers x, y, and z are defined as described in figure 4-4 . figure 4-4. the x-, y-, and z-registers in the different addressing modes these address registers have functions as fixed displacement, automatic increment, and automatic decrement (see the instruction set reference for details). 4.4.6 stack pointer the stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. the stack pointer register always points to the top of the stack. note that the stack is implemented as growing from higher memory loca- tions to lower memory locations. this implies that a stack push command decreases the stack pointer. the stack pointer points to the data sram stack area where the subroutine and interrupt stacks are located. this stack space in the data sram must be defined by the program before any subroutine calls are executed or interrupts are enabled. the stack pointer must be set to point above 0x0100, preferably ramend. the st ack pointer is decremented by one when data is pushed onto the stack with the push instru ction, and it is decremented by two when the return address is pushed onto the stack with subroutine call or interrupt. the stack pointer is incremented by one when data is popped from the stack with the pop instruction, and it is incre- mented by two when data is popped from the stack with return from subroutine ret or return from interrupt reti. 15 xh xl 0 x-register 7 0 7 0 r27 (0x1b) r26 (0x1a) 15 yh yl 0 y-register 7 0 7 0 r29 (0x1d) r28 (0x1c) 15 zh zl 0 z-register 7 0 7 0 r31 (0x1f) r30 (0x1e) 36 4921e?auto?09/09 ata6602/ata6603 the avr stack pointer is implemented as two 8- bit registers in the i/o space. the number of bits actually used is implementation dependent. note that the data space in some implementa- tions of the avr architecture is so small that only spl is needed. in this case, the sph register will not be present. 4.4.7 instruction execution timing this section describes the general access timi ng concepts for instruction execution. the avr cpu is driven by the cpu clock clk cpu , directly generated from the selected clock source for the chip. no internal clo ck division is used. figure 4-5 shows the parallel instruction fetches and instruction executions enabled by the har- vard architecture and the fast-access register file concept. this is the basic pipelining concept to obtain up to 1 mips per mhz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit. figure 4-5. the parallel instruction fetches and instruction executions figure 4-6 on page 37 shows the internal timing concept for the register file. in a single clock cycle an alu operation using two register operands is executed, and the result is stored back to the destination register. bit 151413121110 9 8 sp15 sp14 sp13 sp12 sp11 sp10 sp9 sp8 sph sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 spl 76543210 read/write r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w r/w initial value ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend ramend clk cpu 1st instruction fetch 1st instruction execute 2nd instruction fetch 2nd instruction execute 3rd instruction fetch 3rd instruction execute 4th instruction fetch t1 t2 t3 t4 37 4921e?auto?09/09 ata6602/ata6603 figure 4-6. single cycle alu operation 4.4.8 reset and interrupt handling the avr provides several different interrupt sources. these interrupts and the separate reset vector each have a separate program vector in the program memory space. all interrupts are assigned individual enable bits which must be written logic one together with the global interrupt enable bit in the status register in orde r to enable the interrupt. depending on the program counter value, interrupts may be automatically disabled when boot lock bits blb02 or blb12 are programmed. this feature improves software security. see section ?memory programming? on page 298 for details. the lowest addresses in the program memory space are by default defined as the reset and interrupt vectors. the complete list of vectors is shown in ?interrupts? on page 77 . the list also determines the priority levels of the different interrupts. the lower the address the higher is the priority level. reset has the highest priority, and next is int0 ? the external interrupt request 0. the interrupt vectors can be moved to the start of the boot flash section by setting the ivsel bit in the mcu control r egister (mcucr). refer to ?interrupts? on page 77 for more information. the reset vector can also be moved to the start of the boot flash section by programming the bootrst fuse (see ?boot loader support ? read-while-write self-programming, ata6602 and ata6603? on page 282 ). when an interrupt occurs, the global interrupt enable i-bit is cleared and all interrupts are dis- abled. the user software can write logic one to the i-bit to enable nested interrupts. all enabled interrupts can then interrupt the current interrupt routine. the i-bit is automatically set when a return from interrupt instruction ? reti ? is executed. there are basically two types of interrupts. the fi rst type is triggered by an event that sets the interrupt flag. for these interrupts, the program counter is vectored to the actual interrupt vec- tor in order to execute the interrupt handling routine, and hardware clears the corresponding interrupt flag. interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. if an interrupt condition occurs while the corresponding interrupt enable bit is cleared, the interrupt fl ag will be set and remember ed until the interrupt is enabled, or the flag is cleared by software. similarly, if one or more interrupt conditions occur while the global interrupt enable bit is clea red, the corres ponding interrupt fl ag(s) will be set and remembered until the global interrupt enable bit is set, and will then be exec uted by order of priority. the second type of interrupts will trigger as long as the interrupt condition is present. these interrupts do not necessarily have interrupt flags. if the interrupt condition disappears before the interrupt is enabled, the in terrupt will not be triggered. when the avr exits from an inte rrupt, it will always retu rn to the main pr ogram and execute one more instruction be fore any pending interrupt is served. total execution time register operands fetch alu operation execute result write back t1 t2 t3 t4 clk cpu 38 4921e?auto?09/09 ata6602/ata6603 note that the status register is not automatica lly stored when entering an interrupt routine, nor restored when returning from an interrupt routine. this must be handled by software. when using the cli instruction to disable interrupts, the interrup ts will be immediately disabled. no interrupt will be executed af ter the cli instruction, even if it occurs simultaneously with the cli instruction. the following example shows how this can be used to avoid interrupts during the timed eeprom write sequence. when using the sei instruction to enable interr upts, the instruction following sei will be exe- cuted before any pending interrupts, as shown in this example. 4.4.8.1 interrupt response time the interrupt execution response for all the enabl ed avr interrupts is four clock cycles mini- mum. after four clock cycles the program vector address for the actual interrupt handling routine is executed. during this four clock cycle period, the program counter is pushed onto the stack. the vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. if an interrupt occurs during execution of a multi- cycle instruction, this in struction is completed before the interrupt is served. if an interrupt occurs when the mcu is in sleep mode, the interrupt execution response time is increased by four clock cycles. this increase comes in addition to the start-up time from the selected sleep mode. a return from an interrupt handling routine take s four clock cycles. during these four clock cycles, the program counter (two bytes) is popped back from the stack, the stack pointer is incremented by two, and the i-bit in sreg is set. assembly code example in r16, sreg ; store sreg value cli ; disable interrupts during timed sequence sbi eecr, eempe ; start eeprom write sbi eecr, eepe out sreg, r16 ; restore sreg value (i-bit) c code example char csreg; csreg = sreg; /* store sreg value */ /* disable interrupts during timed sequence */ _cli(); eecr |= (1< 40 4921e?auto?09/09 ata6602/ata6603 figure 4-8. program memory map, ata6602/ata6603 0x0000 0x0fff/0x1fff program memory application flash section boot flash section 41 4921e?auto?09/09 ata6602/ata6603 4.5.2 sram data memory figure 4-9 shows how the ata6602/ata660 3 sram memory is organized. the ata6602/ata6603 is a complex microcontroller with more peripheral units than can be supported within the 64 locations reserved in the opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. the lower 768/1280/1280 data memory locations address both the register file, the i/o mem- ory, extended i/o memory, and the internal data sram. the first 32 locations address the register file, the next 64 location the standard i/o memory, then 160 locations of extended i/o memory, and the next 512/1024/1024 locations address the internal data sram. the five different addressing modes for the data memory cover: direct, indirect with displace- ment, indirect, indirect with pre-decrement, and indirect with post-increment. in the register file, registers r26 to r31 feature the indirect addressing pointer registers. the direct addressing reaches the entire data space. the indirect with displacement mode reaches 63 address locations from the base address given by the y- or z-register. when using register indirect addressing modes with automatic pre-decrement and post-incre- ment, the address registers x, y, and z are decremented or incremented. the 32 general purpose working registers, 64 i /o registers, 160 extended i/o registers, and the 512/1024/1024 bytes of internal data sram in the ata6602/ata6603 are all accessible through all these addressing modes. the register file is described in ?general purpose regis- ter file? on page 34 . figure 4-9. data memory map 32 registers 64 i/o registers internal sram (512/1024/1024 x 8) 0x0000 - 0x001f 0x0020 - 0x005f 0x02ff/0x04ff/0x04f f 0x0060 - 0x00ff data memory 160 ext i/o reg. 0x0100 42 4921e?auto?09/09 ata6602/ata6603 4.5.2.1 data memory access times this section describes the general access timi ng concepts for internal memory access. the internal data sram access is performed in two clk cpu cycles as described in figure 4-10 . figure 4-10. on-chip data sram access cycles 4.5.3 eeprom data memory the ata6602/ata6603 cont ains 512 bytes of data eeprom memory. it is organized as a sep- arate data space, in which single bytes can be read and written. the eeprom has an endurance of at least 100,000 write/erase cycles. the access between the eeprom and the cpu is described in the following, specif ying the eeprom address registers, the eeprom data register, and the eeprom control register. the section ?memory programming? on page 298 contains a detailed description on eeprom programming in spi or parallel programming mode. 4.5.3.1 eeprom read/write access the eeprom access registers are accessible in the i/o space. the write access time for the eeprom is given in table 4-3 on page 45 . a self-timing function, however, lets the user software detect when the nex t byte can be written. if the user code con- tains instructions that write the eeprom, some precautions must be taken. in heavily filtered power supplies, v cc is likely to rise or fall slowly on power-up/down. this causes the device for some period of time to run at a voltage lower than specified as minimum for the clock frequency used. see ?preventing eeprom corruption? on page 47 for details on how to avoid problems in these situations. in order to prevent unintentional eeprom writes, a specific write procedure must be followed. refer to the description of the eeprom control regist er for details on this. when the eeprom is read, the cpu is halted for fo ur clock cycles before the next in struction is executed. when the eeprom is written, the cp u is halted for two clock cycles before the next instruction is executed. clk cpu wr rd data data address address valid t1 t2 t3 compute address read write memory access instruction next instruction 43 4921e?auto?09/09 ata6602/ata6603 4.5.3.2 the eeprom address register ? eearh and eearl ? bits 15..9 ? res: reserved bits these bits are reserved bits in the ata 6602/ata6603 and will always read as zero. ? bits 8..0 ? eear8..0: eeprom address the eeprom address registers ? eearh a nd eearl specify the eeprom address in the 512 bytes eeprom sp ace. the eeprom data bytes ar e addressed linea rly between 0 and 255/511/511. the initial value of eear is undefined. a proper value must be written before the eeprom may be accessed. eear8 is an unused bit in ata6602/ata660 3 and must always be written to zero. 4.5.3.3 the eeprom data register ? eedr ? bits 7..0 ? eedr7.0: eeprom data for the eeprom write operation, the eedr register co ntains the data to be written to the eeprom in the address given by the eear re gister. for the eeprom read operation, the eedr contains the data read out from the eeprom at the add ress given by eear. 4.5.3.4 the eeprom control register ? eecr ? bits 7..6 ? res: reserved bits these bits are reserved bits in the at a6602/ata6603 and will always read as zero ? bits 5, 4 ? eepm1 and eepm0: eeprom programming mode bits the eeprom programming m ode bit setting defines which programming action that will be triggered when writing eepe. it is possible to program data in one atomic operation (erase the old value and program the new value) or to split the erase and write operations in two different operations. bit 151413121110 9 8 ???????eear8eearh eear7 eear6 eear5 eear4 eear3 eear2 eear1 eear0 eearl 76543210 read/write r r rrrrrr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value0000000x xxxxxxxx bit 76543210 msb lsb eedr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ? eepm1 eepm0 eerie eempe eepe eere eecr read/write r r r/w r/w r/w r/w r/w r/w initial value 0 0 x x 0 0 x 0 44 4921e?auto?09/09 ata6602/ata6603 the programming times for the different modes are shown in table 4-2 . while eepe is set, any write to eepmn will be ignored. during reset, the eepmn bits will be reset to 0b00 unless the eeprom is busy programming. ? bit 3 ? eerie: eeprom ready interrupt enable writing eerie to one enables the eeprom ready interrupt if the i bit in sreg is set. writ- ing eerie to zero disables the interrupt. the eeprom ready interrupt generates a constant interrupt when eepe is cleared. ? bit 2 ? eempe: eeprom master write enable the eempe bit determines whether setting eepe to one causes the eepr om to be written. when eempe is set, setting eepe within four clock cycles will write data to the eeprom at the selected address if eempe is zero, sett ing eepe will have no effect. when eempe has been written to one by software, hardware clears the bit to zero after four clock cycles. see the description of the eepe bit for an eeprom write procedure. ? bit 1 ? eepe: eeprom write enable the eeprom write enable signal eepe is th e write strobe to th e eeprom. when address and data are correctly set up, th e eepe bit must be written to one to write the value into the eeprom. the eempe bit must be written to one before a logical one is written to eepe, otherwise no eeprom write takes place. the following procedure should be followed when writing the eeprom (the order of steps 3 and 4 is not essential): 1. wait until eepe becomes zero. 2. wait until selfprgen in spmcsr becomes zero. 3. write new eeprom address to eear (optional). 4. write new eeprom data to eedr (optional). 5. write a logical one to the eempe bit while writing a zero to eepe in eecr. 6. within four clock cycles after sett ing eempe, write a logical one to eepe. the eeprom can not be programmed during a cpu write to the flash memory. the soft- ware must check that the flash programming is completed before initiating a new eeprom write. step 2 is only relevant if the software contains a boot loader allowing the cpu to pro- gram the flash. if the flash is never being updated by the cpu, step 2 can be omitted. see ?boot loader support ? read-while-write self-programming, ata6602 and ata6603? on page 282 for details about boot programming. caution: an interrupt between step 5 and step 6 will make the write cycle fail, since the eeprom master write enable will time-out. if an interrupt routine accessing the eeprom is interrupting another eeprom access, th e eear or eedr register will be modified, causing the inte rrupted eeprom access to fail. it is re commended to have the global inter- rupt flag cleared during all the steps to avoid these problems. table 4-2. eeprom mode bits eepm1 eepm0 programming time operation 0 0 3.4 ms erase and write in one operation (atomic operation) 0 1 1.8 ms erase only 1 0 1.8 ms write only 1 1 ? reserved for future use 45 4921e?auto?09/09 ata6602/ata6603 when the write access time has elapsed, the eepe bit is cleared by hardware. the user software can poll this bit a nd wait for a zero before writ ing the next byte. when eepe has been set, the cpu is halted for two cycles before the next instruction is executed. ? bit 0 ? eere: eeprom read enable the eeprom read enable signal eere is the read strobe to the eeprom. when the cor- rect address is set up in the eear register, the eere bit must be written to a logic one to trigger the eeprom read. the eeprom read access takes one instruction, and the requested data is available immediately. when the eeprom is read, the cpu is halted for four cycles before the next instruction is executed. the user should poll th e eepe bit before starting the read o peration. if a write operation is in progress, it is neither possi ble to read the eeprom, nor to change the eear register. the calibrated oscillator is used to time the eeprom accesses. table 4-3 lists the typical programming time for eeprom access from the cpu. the following code examples show one assembly and one c function for writing to the eeprom. the examples assume that interrupts are controlled (e.g. by dis abling interrupts glob- ally) so that no interrupts will occur during ex ecution of these functions. the examples also assume that no flash boot loader is present in the software. if such code is present, the eeprom write function must also wait fo r any ongoing spm co mmand to finish. table 4-3. eeprom programming time symbol number of calibrated rc oscillator cycles typ programming time eeprom write (from cpu) 26,368 3.3 ms 46 4921e?auto?09/09 ata6602/ata6603 the next code examples show assembly and c functions for reading the eeprom. the exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. assembly code example eeprom_write: ; wait for completion of previous write sbic eecr,eepe rjmp eeprom_write ; set up address (r18:r17) in address register out eearh, r18 out eearl, r17 ; write data (r16) to data register out eedr,r16 ; write logical one to eempe sbi eecr,eempe ; start eeprom write by setting eepe sbi eecr,eepe ret c code example void eeprom_write( unsigned int uiaddress, unsigned char ucdata) { /* wait for completion of previous write */ while(eecr & (1< 49 4921e?auto?09/09 ata6602/ata6603 4.6 system clock and clock options 4.6.1 clock systems and their distribution figure 4-11 presents the principal clock systems in the avr and their distribution. all of the clocks need not be active at a given time. in order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ?power management and sleep modes? on page 60 . the clock systems are detailed below. figure 4-11. clock distribution 4.6.1.1 cpu clock ? clk cpu the cpu clock is routed to parts of the system concerned with operation of the avr core. examples of such modules are the general pur pose register file, the status register and the data memory holding the stack pointer. halting the cpu clock inhibits the core from performing general operations and calculations. 4.6.1.2 i/o clock ? clk i/o the i/o clock is used by the majority of the i/o modules, like timer/counters, spi, and usart. the i/o clock is also used by the external inte rrupt module, but note that some external inter- rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the i/o clock is halted. also note that start condition detection in the usi module is carried out asynchro- nously when clk i/o is halted, twi address recognition in all sleep modes. 4.6.1.3 flash clock ? clk flash the flash clock controls operation of the flash in terface. the flash clock is usually active simul- taneously with the cpu clock. general i/o modules asynchronous timer/counter cpu core ram clk i/o clk asy avr clock control unit clk cpu flash and eeprom clk flash source clock watchdog timer watchdog oscillator reset logic clock multiplexer watchdog clock calibrated rc oscillator timer/counter oscillator crystal oscillator low-frequency crystal oscillator external clock adc clk adc system clock prescaler 50 4921e?auto?09/09 ata6602/ata6603 4.6.1.4 asynchronous timer clock ? clk asy the asynchronous timer clock al lows the asynchronous timer/c ounter to be clocked directly from an external clock or an external 32 khz clock crystal. the dedicated clock domain allows using this timer/counter as a real-time counter even when the device is in sleep mode. 4.6.1.5 adc clock ? clk adc the adc is provided with a dedicated clock domain. this allows halting the cpu and i/o clocks in order to reduce noise generated by digital circuitry. this gives more accurate adc conversion results. 4.6.2 clock sources the device has the following clock source options, selectable by flash fuse bits as shown below. the clock from the selected source is input to the avr clock generator, and routed to the appropriate modules. note: 1. for all fuses ?1? means unprogrammed while ?0? means programmed. 4.6.2.1 default clock source the device is shipped with inte rnal rc oscillator at 8.0mhz a nd with the fuse ckdiv8 pro- grammed, resulting in 1.0mhz system clock. th e startup time is set to maximum and time-out period enabled. (cksel = "0010", su t = "10", ckdiv8 = "0"). th e default setti ng ensures that all users can make their desired clock source se tting using any available programming interface. 4.6.2.2 clock startup sequence any clock source needs a sufficient v cc to start oscillating and a minimum number of oscillating cycles before it can be considered stable. to ensure sufficient v cc , the device issues an internal reset with a time-out delay (t tout ) after the device reset is released by all other reset sources. the section ?system control and reset? on page 66 describes the start conditions for the internal reset. the delay (t tout ) is timed from the watchdog oscill ator and the number of cycles in the delay is set by the sutx and ckselx fuse bits. the selectable delays are shown in table 4-5 on page 51 . the frequency of the watchdog oscillator is voltage dependent as shown in ?register summary? on page 342 . table 4-4. device clocking options select (1) device clocking option cksel3..0 low power crystal oscillator 1111 - 1000 full swing crystal oscillator 0111 - 0110 low frequency crystal oscillator 0101 - 0100 internal 128 khz rc oscillator 0011 calibrated internal rc oscillator 0010 external clock 0000 reserved 0001 51 4921e?auto?09/09 ata6602/ata6603 main purpose of the delay is to keep the avr in reset until it is supplied with minimum v cc . the delay will not monitor t he actual voltage and it w ill be required to select a delay longer than the v cc rise time. if this is not possible, an internal or external brown-out detection circuit should be used. a bod circuit will ensure sufficient v cc before it releases the reset, and the time-out delay can be disabled. disabling the time-out delay wi thout utilizing a brown-out detection circuit is not recommended. the oscillator is required to osc illate for a minimum number of cycl es before the clock is consid- ered stable. an inte rnal ripple counter monito rs the oscillator output cl ock, and keep s the internal reset active for a given number of clock cycl es. the reset is then released and the device will start to execute. the recommend ed oscillator start-up time is dependent on the clock type, and varies from 6 cycles for an externally applied clock to 32k cycles for a low frequency crystal. the start-up sequence for the clock includes both the time-out delay and the start-up time when the device starts up from reset. when starting up from power-save or power-down mode, v cc is assumed to be at a sufficient level and only the start-up time is included. 4.6.3 low power crystal oscillator pins xtal1 and xtal2 are input and output, respec tively, of an invertin g amplifier which can be configured for use as an on-c hip oscillator, as shown in figure 4-12 . either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a low power oscillator, with reduced voltage swing on the xtal2 out- put. it gives the lowest power consumption, but is not capable of driving other clock inputs, and may be more susceptible to noise in noisy environments. in these cases, refer to the ?full swing crystal oscillator? on page 53 . c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 4-6 on page 52 . for ceramic resonators, the capacitor val- ues given by the manufacturer should be used. figure 4-12. crystal oscillator connections the low power oscillator c an operate in three diff erent modes, each optimi zed for a specific fre- quency range. the operating mode is selected by the fuses cksel3..1 as shown in table 4-6 on page 52 . table 4-5. number of watchdog oscillator cycles typ time-out (v cc = 5.0v) typ time-out (v cc = 3.0v) number of cycles 0 ms 0 ms 0 4.1 ms 4.3 ms 4k (4,096) 65 ms 69 ms 8k (8,192) xtal2 xtal1 gnd c2 c1 52 4921e?auto?09/09 ata6602/ata6603 notes: 1. the frequency ranges are preliminary values. actual values are tbd. 2. this option should not be used with crystals, only with ceramic resonators. 3. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets th e frequency specification of the device. the cksel0 fuse together with the sut1..0 fuses select the start-up times as shown in table 4-7 . notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start- up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with cerami c resonators and will ensure frequency stability at start-up. they can also be used with crystal s when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. table 4-6. low power crystal osc illator operating modes (3) frequency range (1) (mhz) cksel3..1 recommended range for capacitors c1 and c2 (pf) 0.4 - 0.9 100 (2) ? 0.9 - 3.0 101 12 - 22 3.0 - 8.0 110 12 - 22 8.0 - 16.0 111 12 - 22 table 4-7. start-up times for the low power cr ystal oscillator clock selection oscillator source/ power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 ceramic resonator, fast rising power 258 ck 14ck + 4.1 ms (1) 000 ceramic resonator, slowly rising power 258 ck 14ck + 65 ms (1) 001 ceramic resonator, bod enabled 1k ck 14ck (2) 010 ceramic resonator, fast rising power 1k ck 14ck + 4.1 ms (2) 011 ceramic resonator, slowly rising power 1k ck 14ck + 65 ms (2) 100 crystal oscillator, bod enabled 16k ck 14ck 1 01 crystal oscillator, fast rising power 16k ck 14ck + 4.1 ms 1 10 crystal oscillator, slowly rising power 16k ck 14ck + 65 ms 1 11 53 4921e?auto?09/09 ata6602/ata6603 4.6.4 full swing crystal oscillator pins xtal1 and xtal2 are input and output, respec tively, of an invertin g amplifier which can be configured for use as an on-chip oscillator, as shown in figure 4-12 on page 51 . either a quartz crystal or a ceramic resonator may be used. this crystal oscillator is a full s wing oscillator, wit h rail-to-rail swing on th e xtal2 output. this is useful for driving other clock inputs and in noisy environments. the current consumption is higher than the ?low power crystal os cillator? on page 51 . note that the full swing crystal oscillator will only operate for v cc = 2.7 - 5.5v. c1 and c2 should always be equal for both crystals and resonators. the optimal value of the capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the electromagnetic noise of the environment. some initial guidelines for choosing capacitors for use with crystals are given in table 4-9 on page 54 . for ceramic resonators, the capacitor val- ues given by the manufacturer should be used. the operating mode is selected by the fuses cksel3..1 as shown in table 4-8 . notes: 1. the frequency ranges are preliminary values. actual values are tbd. 2. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets th e frequency specification of the device. figure 4-13. crystal oscillator connections table 4-8. full swing crystal osc illator operating modes (2) frequency range (1) (mhz) cksel3..1 recommended range for capacitors c1 and c2 (pf) 0.4 - 20 011 12 - 22 xtal2 xtal1 gnd c2 c1 54 4921e?auto?09/09 ata6602/ata6603 notes: 1. these options should only be used when not operating close to the maximum frequency of the device, and only if frequency stability at start- up is not important for the application. these options are not suitable for crystals. 2. these options are intended for use with cerami c resonators and will ensure frequency stability at start-up. they can also be used with crystal s when not operating close to the maximum fre- quency of the device, and if frequency stability at start-up is not important for the application. 4.6.5 low frequency crystal oscillator the device can utilize a 32.768 khz watch crystal as clock source by a dedicated low fre- quency crystal oscillator. the crysta l should be connected as shown in figure 4-12 on page 51 . when this oscillator is selected, start-up times are determined by the sut fuses and cksel0 as shown in table 4-10 . note: 1. these options should only be used if frequen cy stability at start-up is not important for the application. table 4-9. start-up times for the full swing crystal oscillator clock selection oscillator source/ power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 ceramic resonator, fast rising power 258 ck 14ck + 4.1 ms (1) 000 ceramic resonator, slowly rising power 258 ck 14ck + 65 ms (1) 001 ceramic resonator, bod enabled 1k ck 14ck (2) 010 ceramic resonator, fast rising power 1k ck 14ck + 4.1 ms (2) 011 ceramic resonator, slowly rising power 1k ck 14ck + 65 ms (2) 100 crystal oscillator, bod enabled 16k ck 14ck 1 01 crystal oscillator, fast rising power 16k ck 14ck + 4.1 ms 1 10 crystal oscillator, slowly rising power 16k ck 14ck + 65 ms 1 11 table 4-10. start-up times for the lo w frequency crystal oscillator clock selection power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) cksel0 sut1..0 bod enabled 1k ck 14ck (1) 000 fast rising power 1k ck 14ck + 4.1 ms (1) 001 slowly rising power 1k ck 14ck + 65 ms (1) 010 reserved 0 11 bod enabled 32k ck 14ck 1 00 fast rising power 32k ck 14ck + 4.1 ms 1 01 slowly rising power 32k ck 14ck + 65 ms 1 10 reserved 1 11 55 4921e?auto?09/09 ata6602/ata6603 4.6.6 calibrated internal rc oscillator the calibrated intern al rc oscillator by default provides a 8.0 mhz clock. the frequency is nom- inal value at 3v and 25c. the device is shipped with the ckdiv8 fuse programmed. see ?system clock prescaler? on page 58 for more details. this clock may be selected as the system clock by programming the cksel fuses as shown in table 4-11 . if selected, it will operate with no external components. during reset, hardware loads the calibration byte into the osccal register and thereby automa tically calibrates the rc oscillator. at 3v and 25 c, this calibration gives a frequency of 8 mhz 1%. the tolerance of th e internal rc oscillato r remains better than 10% within the whole automotive temperature and voltage ranges (2.7v to 5.5v, ?40c to +125c). the oscillator can be calibrated to any frequency in the range 7.3 - 8.1 mhz within 1% accuracy, by changing the osccal register . when this oscillator is used as the chip clock, the watchdog oscillator will still be us ed for the watchdog timer and for the reset time-out. for more information on the pre-programmed calibration value (see ?calibration byte? on page 302 ). notes: 1. the device is shipped with this option selected. 2. the frequency ranges are preliminary values. actual values are tbd. 3. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. when this oscillator is select ed, start-up times are determined by the sut fuses as shown in table 4-12 . note: 1. if the rstdisbl fuse is programmed , this start-up time will be increased to 14ck + 4.1 ms to ensure programming mode can be entered. 2. the device is shipped wit h this option selected. table 4-11. internal calibrated rc o scillator operating modes (1)(3) frequency range (2) (mhz) cksel3..0 7.3 - 8.1 0010 table 4-12. start-up times for the internal calib rated rc oscillato r clock selection power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6 ck 14ck (1) 00 fast rising power 6 ck 14ck + 4.1 ms 01 slowly rising power 6 ck 14ck + 65 ms (2) 10 reserved 11 56 4921e?auto?09/09 ata6602/ata6603 4.6.6.1 oscillator calibrati on register ? osccal ? bits 7..0 ? cal7..0: oscillator calibration value the oscillator calibration register is used to trim the calibra ted internal rc oscillator to remove process variations from the oscillator frequency. the factory-calibrated value is automatically written to this register dur ing chip reset, giving an oscillator frequency of 8.0 mhz at 25c. the application software can write this regist er to change the oscillator fre- quency. the oscillator can be calibrated to any frequency in the range 7.3 - 8.1 mhz within 1% accuracy. calibration outside that range is not guaranteed. note that this oscilla tor is used to time eeprom and fl ash write accesses, and these write times will be affected accordingly. if the eepr om or flash are written, do not calibrate to more than 8.8 mhz. otherwise, the eeprom or flash write may fail. the cal7 bit determines the range of operation for the oscillator. setting this bit to 0 gives the lowest frequency range, setting this bit to 1 gives the highest frequency range. the two frequency ranges are overlapping, in other wo rds a setting of osccal = 0x7f gives a higher frequency than osccal = 0x80. the cal6..0 bits are used to tune the frequency within the selected range. a setting of 0x00 gives the lowest frequency in that range, and a setting of 0x7f gives the highest frequency in the range. incrementing cal6..0 by 1 will give a frequency increment of less than 2% in the frequency range 7.3 - 8.1 mhz. 4.6.7 128 khz internal oscillator the 128 khz internal oscillator is a low power oscillator providing a clock of 128 khz. the fre- quency is nominal at 3v and 25 c. this clock may be select as the system clock by programming the c ksel fuses to ?11? as shown in table 4-13 . note: 1. the frequency is preliminary value. actual value is tbd. when this clock source is sele cted, start-up times are determined by the sut fuses as shown in table 4-14 on page 57 . bit 76543210 cal7 cal6 cal5 cal4 cal3 cal2 cal1 cal0 osccal read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value device specific calibration value table 4-13. 128 khz internal osc illator operating modes nominal frequency cksel3..0 128 khz 0011 57 4921e?auto?09/09 ata6602/ata6603 note: 1. if the rstdisbl fuse is programmed , this start-up time will be increased to 14ck + 4.1 ms to ensure programming mode can be entered. 4.6.8 external clock the device can utilize a external clock source as shown in figure 4-14 . to run the device on an external clock, the c ksel fuses must be pr ogrammed as shown in table 4-15 . notes: 1. the frequency ranges are preliminary values. actual values are tbd. 2. if 8 mhz frequency exceeds the specification of the device (depends on v cc ), the ckdiv8 fuse can be programmed in order to divide the internal frequency by 8. it must be ensured that the resulting divided clock meets th e frequency specification of the device. figure 4-14. external clock drive configuration when this clock source is sele cted, start-up times are determined by the sut fuses as shown in table 4-16 . table 4-14. start-up times for the 128 k hz internal oscillator power conditions start-up time from power-down and power-save additional delay from reset sut1..0 bod enabled 6 ck 14ck (1) 00 fast rising power 6 ck 14ck + 4 ms 01 slowly rising power 6 ck 14ck + 64 ms 10 reserved 11 table 4-15. full swing crystal osc illator operating modes (2) frequency range (1) (mhz) cksel3..0 recommended range for capacitors c1 and c2 (pf) 0 - 100 0000 12 - 22 table 4-16. start-up times for the external clock selection power conditions start-up time from power-down and power-save additional delay from reset (v cc = 5.0v) sut1..0 bod enabled 6 ck 14ck 00 fast rising power 6 ck 14ck + 4.1 ms 01 slowly rising power 6 ck 14ck + 65 ms 10 reserved 11 nc external clock signal xtal2 xtal1 gnd 58 4921e?auto?09/09 ata6602/ata6603 when applying an external clock, it is required to avoid sudden changes in the applied clock fre- quency to ensure stable operation of the mcu. a variation in frequency of more than 2% from one clock cycle to the next can lead to unpredict able behavior. if changes of more than 2% is required, ensure that the mcu is kept in reset during the changes. note that the system clock prescaler can be used to implement run-time changes of the internal clock frequency while still ensuri ng stable operation. refer to ?system clock prescaler? on page 58 for details. 4.6.9 clock output buffer the device can output the system clock on t he clko pin. to enable the output, the ckout fuse has to be programmed. this mode is suitable when the chip clock is used to drive other cir- cuits on the system. the clock also will be output during reset, and the normal operation of i/o pin will be overridden when the fu se is programmed. an y clock source, includi ng the internal rc oscillator, can be selected when the clock is out put on clko. if the system clock prescaler is used, it is the divided system clock that is output. 4.6.10 timer/counter oscillator the device can operate its timer/counter2 from an external 32.768 khz watch crystal or a exter- nal clock source. the timer/counter oscillat or pins (tosc1 and tosc2) are shared with xtal1 and xtal2. this means that the timer/ counter oscillator can only be used when an internal rc oscillator is selected as syste m clock source. see figure 4-12 on page 51 for crystal connection. applying an external clock source to tosc1 requi res extclk in the assr register written to logic one. see ?asynchronous operation of the timer/counter? on page 178 for further descrip- tion on selecting external clock as input instead of a 32 khz crystal. 4.6.11 system clock prescaler the ata6602/ata6603 has a system clock presca ler, and the system clock can be divided by setting the ?clock prescale register ? clkpr? on page 59 7. this feature can be used to decrease the system clock frequency and the power consumption when the requirement for pro- cessing power is low. this can be used with all cl ock source options, and it will affect the clock frequency of the cpu and all synchronous peripherals. clk i/o , clk adc , clk cpu , and clk flash are divided by a factor as shown in table 4-20 on page 68 . when switching between prescaler settings, the system clock prescaler ensures that no glitches occurs in the clock system. it also ensures that no intermediate frequency is higher than neither the clock frequency corresponding to the previous setting, nor the clock frequency corre- sponding to the new setting. the ripple counter that implements the prescaler runs at the frequency of the undivided clock, which may be faster than the cpu's clock frequency. hence, it is not possible to determine the state of the prescaler - even if it were readable, and the exact time it takes to switch from one clock division to the other cannot be exactly predicted. from the time the clkps values are written, it takes between t1 + t2 and t1 + 2 * t2 before the new clock frequency is active. in this interval, 2 acti ve clock edges are produced. here, t1 is the pre- vious clock period, and t2 is the period corresponding to the new prescaler setting. 59 4921e?auto?09/09 ata6602/ata6603 to avoid unintentional changes of clock frequency, a special write procedure must be followed to change the clkps bits: 1. write the clock prescaler change enable (clkpce) bit to one and all other bits in clkpr to zero. 2. within four cycles, write the desired va lue to clkps while writing a zero to clkpce. interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 4.6.11.1 clock presca le register ? clkpr ? bit 7 ? clkpce: clock prescaler change enable the clkpce bit must be written to logic one to enable change of the clkps bits. the clk- pce bit is only updated when the other bits in clkpr are simultaneously written to zero. clkpce is cleared by hardware four cycles after it is written or when clkps bits are writ- ten. rewriting the clkpce bit within this time-out period does neither extend the time-out period, nor clear the clkpce bit. ? bits 3..0 ? clkps3..0: clock prescaler select bits 3 - 0 these bits define the division factor between th e selected clock source and the internal sys- tem clock. these bits can be written run-time to vary the clock frequency to suit the application requirements. as the divider divides the master clock input to the mcu, the speed of all synchronous peripherals is reduce d when a division factor is used. the division factors are given in table 4-17 on page 60 . the ckdiv8 fuse determines the initial val ue of the clkps bits. if ckdiv8 is unpro- grammed, the clkps bits will be reset to ?0000?. if ckdiv8 is programmed, clkps bits are reset to ?0011?, giving a division factor of 8 at start up. this feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditio ns. note that any value can be written to the clkps bits regardless of the ckdiv8 fuse setting. the application software must ensure that a suffi- cient division factor is chosen if the selected clock source has a higher frequency than the maximum frequency of the device at the present operating conditions. the device is shipped with the ckdiv8 fuse programmed. bit 76543210 clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 clkpr read/write r/w r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 60 4921e?auto?09/09 ata6602/ata6603 4.7 power management and sleep modes sleep modes enable the application to shut down unused modules in the mcu, thereby saving power. the avr provides various sleep modes allowing the user to tailor the power consump- tion to the application?s requirements. to enter any of the five sleep modes, the se bit in smcr must be written to logic one and a sleep instruction must be executed. the sm2, sm1, and sm0 bits in the smcr register select which sleep mode (idle, adc noise reduction, power-down, power-save, or standby) will be activated by the sleep instruction. see table 4-18 on page 61 for a summary. if an enabled interrupt occurs while the mcu is in a sleep mode, the mcu wakes up. the mcu is then halted for four cycles in addition to t he start-up time, executes the interrupt routine, and resumes exe- cution from the instruction following sleep. the contents of the register file and sram are unaltered when the device wakes up from sleep. if a reset occurs during sleep mode, the mcu wakes up and executes from the reset vector. figure 4-11 on page 49 presents the different clock systems in the ata6602/ata6603, and their distribution. the figure is helpful in selecting an appropriate sleep mode. table 4-17. clock prescaler select clkps3 clkps2 clkps1 clkps0 clock division factor 0000 1 0001 2 0010 4 0011 8 0100 16 0101 32 0110 64 0111 128 1000 256 1001 reserved 1010 reserved 1011 reserved 1100 reserved 1101 reserved 1110 reserved 1111 reserved 61 4921e?auto?09/09 ata6602/ata6603 4.7.1 sleep mode control register ? smcr the sleep mode control register contains control bits for power management. ? bits 7..4 res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bits 3..1 ? sm2..0: sleep mode select bits 2, 1, and 0 these bits select between the five available sleep modes as shown in table 4-18 . note: 1. standby mode is only recommended for use with external crystals or resonators. ? bit 0 ? se: sleep enable the se bit must be written to logic one to make the mcu enter the sleep mode when the sleep instruction is exec uted. to avoid the mcu entering the sleep mode unless it is the programmer?s purpose, it is recommended to write the sleep enable (se) bit to one just before the execution of the sl eep instruction and to clear it immediately after waking up. 4.7.2 idle mode when the sm2..0 bits are written to 000, the sleep instruction makes the mcu enter idle mode, stopping the cpu but allowing the spi, usart, analog comparator, adc, 2-wire serial interface, timer/counters, watchdog, and the interrupt system to continue operating. this sleep mode basically halts clk cpu and clk flash , while allowing the ot her clocks to run. idle mode enables the mcu to wake up from external triggered interrupts as well as internal ones like the timer overflow and usart transmit complete interrupts. if wake-up from the analog comparator interrupt is not required, the analog comparator can be powered down by setting the acd bit in the analog comparator control and status regist er ? acsr. this will reduce power consumption in idle mode. if t he adc is enabled, a conversion starts automati- cally when this mode is entered. bit 76543210 ? ? ? ? sm2 sm1 sm0 se smcr read/write r r r r r/w r/w r/w r/w initial value00000000 table 4-18. sleep mode select sm2 sm1 sm0 sleep mode 000idle 0 0 1 adc noise reduction 0 1 0 power-down 0 1 1 power-save 1 0 0 reserved 1 0 1 reserved 1 1 0 standby (1) 1 1 1 reserved 62 4921e?auto?09/09 ata6602/ata6603 4.7.3 adc noise reduction mode when the sm2..0 bits are written to 001, the sleep instruction makes the mcu enter adc noise reduction mode, stopping the cpu but allowing the adc, the external interrupts, the 2-wire serial interface address watch, timer/c ounter2, and the watchdog to continue operating (if enabled). this sleep mode basically halts clk i/o , clk cpu , and clk flash , while allowing the other clocks to run. this improves the noise environment for the ad c, enabling higher resolution measurements. if the adc is enabled, a conversion starts automatically when this mode is entered. apart from the adc conversion complete inte rrupt, only an external reset, a watchdog system reset, a watchdog interrupt, a brown-out reset, a 2-wire serial interface address match, a timer/counter2 interrupt, an spm/eeprom ready interrupt, an external level interrupt on int0 or int1 or a pin change interrupt can wake up the mcu from adc noise reduction mode. 4.7.4 power-down mode when the sm2..0 bits are written to 010, the sleep instruction makes the mcu enter power-down mode. in this mode, th e external oscilla tor is stopped, while th e external interrupts, the 2-wire serial interface address watch, and the watchdog continue operating (if enabled). only an external reset, a watchdog system reset, a watchdog interrupt, a brown-out reset, a 2-wire serial interface address match, an external level interrupt on int0 or int1, or a pin change interrupt can wake up the mcu. this sleep mode basically halts all generated clocks, allowing operation of asynchronous modules only. note that if a level triggered interrupt is used for wake-up from power-down mode, the changed level must be held for some time to wake up the mcu. refer to ?external interrupts? on page 106 for details. when waking up from power-down mode, there is a delay from the wake-up condition occurs until the wake-up becomes effective. this allows the clock to restart and become stable after having been stopped. the wake-up period is defined by the same cksel fuses that define the reset time-out period, as described in ?clock sources? on page 50 . 4.7.5 power-save mode when the sm2..0 bits are written to 011, the sleep instruction makes the mcu enter power-save mode. this mode is identica l to power-down, wi th one exception. if timer/counter2 is e nabled, it will keep running during sleep. the device can wake up from either timer overflow or output compare event from timer/counter2 if the corresponding timer/counter2 interrupt enable bits are set in timsk2, and the global interrupt enable bit in sreg is set. if timer/counter2 is not running, power-down mode is recommended instead of power-save mode. the timer/counter2 can be clocked both synchronously and asynchronously in power-save mode. if timer/counter2 is no t using the asynchronous clock, the timer/counter oscillator is stopped during sleep. if timer/counter2 is not using the synchronous cloc k, the clock source is stopped during sleep. note that even if the synchronous clock is running in power-save, this clock is only available for timer/counter2. 63 4921e?auto?09/09 ata6602/ata6603 4.7.6 standby mode when the sm2..0 bits are 110 and an external crystal/resonator clock option is selected, the sleep instruction makes the mcu enter standby mode. this mode is identical to power-down with the exception that the oscillator is kept running. fr om standby mode, the device wakes up in six clock cycles. notes: 1. only recommended with external crystal or resonator selected as clock source. 2. if timer/counter2 is running in asynchronous mode. 3. for int1 and int0, only level interrupt. 4.7.7 power reduction register the power reduction register, prr, provides a method to stop the clock to individual peripher- als to reduce power consumption. the current state of the peripheral is frozen and the i/o registers can not be read or written. resources used by the peripheral when stopping the clock will remain occupied, hence the perip heral should in most cases be disabled before stopping the clock. waking up a module, which is done by clear ing the bit in prr, puts the module in the same state as before shutdown. module shutdown can be used in idle mode and ac tive mode to significantly reduce the overall power consumption. see ?power-down supply current? on page 328 for examples. in all other sleep modes, the clock is already stopped. table 4-19. active clock domains and wake-up sources in the different sleep modes sleep mode active clock domains oscillators wake-up sources clk cpu clk flash clk io clk adc clk asy main clock source enabled timer oscillator enabled int1, int0 and pin change twi address match timer2 spm/eeprom ready adc wdt other i/o idle x x x x x (2) xxxxxxx adc noise reduction xx x x (2) x (3) xxxxx power-down x (3) xx power-save x x x (3) xx x standby (1) xx (3) xx 64 4921e?auto?09/09 ata6602/ata6603 4.7.7.1 power reduction register - prr ? bit 7 - prtwi: power reduction twi writing a logic one to this bit shuts down the twi by stopping the clock to the module. when waking up the twi again, the twi should be re initialized to ensure proper operation. ? bit 6 - prtim2: power reduction timer/counter2 writing a logic one to this bit shuts down the timer/counter2 module in synchronous mode (as2 is 0). when the timer/counter2 is enabled, operation will continue like before the shutdown. ? bit 5 - prtim0: power reduction timer/counter0 writing a logic one to this bit shuts down the timer/counter0 module. when the timer/counter0 is enabl ed, operation will continue like before the shutdown. ? bit 4 - res: reserved bit this bit is reserved in ata6602/ata6603 and will always read as zero. ? bit 3 - prtim1: power reduction timer/counter1 writing a logic one to this bit shuts down the timer/counter1 module. when the timer/counter1 is enabl ed, operation will continue like before the shutdown. ? bit 2 - prspi: power reduction serial peripheral interface writing a logic one to this bit shuts down the se rial peripheral interface by stopping the clock to the module. when waking up the spi again, th e spi should be re initialized to ensure proper operation. ? bit 1 - prusart0: power reduction usart0 writing a logic one to this bit shuts down th e usart by stopping the clock to the module. when waking up the usart again, the usart s hould be re initialized to ensure proper operation. ? bit 0 - pradc: power reduction adc writing a logic one to this bit shuts down the adc. the adc must be disabled before shut down. the analog comparator cannot use the adc input mux when the adc is shut down. bit 7 6 5 4 3 2 1 0 prtwi prtim2 prtim0 ? prtim1 prspi prusart0 pradc prr read/write r/w r/w r/w r r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 65 4921e?auto?09/09 ata6602/ata6603 4.7.8 minimizing power consumption there are several possibilities to consider when trying to minimi ze the power consumption in an avr controlled system. in general, sleep modes should be used as much as possible, and the sleep mode should be selected so that as few as possible of the device?s functions are operat- ing. all functions not needed shoul d be disabled. in particular, the following modules may need special consideration when trying to achieve the lowest possible power consumption. 4.7.8.1 analog to digital converter if enabled, the adc will be enabled in all sleep modes. to save power, the adc should be dis- abled before entering any sleep mode. when the adc is turned off and on again, the next conversion will be an extended conversion. refer to ?analog-to-digital converter? on page 263 for details on adc operation. 4.7.8.2 analog comparator when entering idle mode, the analog comparator should be disabled if not used. when entering adc noise reduction mode, the analog comparator should be disabled. in other sleep modes, the analog comparator is automatically disabled. however, if the analog comparator is set up to use the internal voltage reference as input, the analog comparator should be disabled in all sleep modes. otherwise, the internal voltage reference will be enabled, independent of sleep mode. refer to ?analog comparator? on page 260 for details on how to configure the analog comparator. 4.7.8.3 brown-out detector if the brown-out detector is not needed by the application, this module should be turned off. if the brown-out detector is enabled by the bo dlevel fuses, it will be enabled in all sleep modes, and hence, always co nsume power. in the deeper sleep modes, this w ill contribute sig- nificantly to the total current consumption. refer to ?brown-out detect ion? on page 69 for details on how to configure the brown-out detector. 4.7.8.4 internal voltage reference the internal voltage referenc e will be enabled when needed by the brown-out de tection, the analog comparator or the adc. if these modules are disabled as described in the sections above, the internal voltage refe rence will be disabled and it w ill not be consuming power. when turned on again, the user must allow the reference to start up before the output is used. if the reference is kept on in sleep mode, the output can be used immediately. refer to ?internal volt- age reference? on page 71 for details on the start-up time. 4.7.8.5 watchdog timer if the watchdog timer is not needed in the application, the module should be turned off. if the watchdog timer is enabled, it will be enabled in all sleep m odes and hence al ways consume power. in the deeper slee p modes, this will contribute signific antly to the total current consump- tion. refer to ?watchdog timer? on page 72 for details on how to configure the watchdog timer. 66 4921e?auto?09/09 ata6602/ata6603 4.7.8.6 port pins when entering a sleep mode, all port pins should be configured to use minimum power. the most important is then to ensure that no pins drive resistive loads. in sleep modes where both the i/o clock (clk i/o ) and the adc clock (clk adc ) are stopped, the input buffers of the device will be disabled. this ensures that no power is consumed by the input logic when not needed. in some cases, the input logic is needed for detec ting wake-up conditions, and it will then be enabled. refer to the section ?digital input enable and sleep modes? on page 92 for details on which pins are enabled. if the input buffer is enabl ed and the input signal is left floating or have an analog signal level close to v cc /2, the input buffer will use excessive power. for analog input pins, the digital input buffer should be disabled at all times. an analog signal level close to v cc /2 on an input pin can cause significant current even in active mode. digital input buffers can be disabled by writing to the digital input disable registers (didr1 and didr0). refer to ?digital input disable register 1 ? didr1? on page 262 and ?digital input dis- able register 0 ? didr0? on page 279 for details. 4.7.8.7 on-chip debug system if the on-chip debug system is enabled by the dwen fuse and the chip enters sleep mode, the main clock source is enabled and hence always consumes power. in the deeper sleep modes, this will contribute significantly to the total current consumption. 4.8 system control and reset 4.8.1 resetting the avr during reset, all i/o registers are set to their initial values, and the program starts execution from the reset vector. for the ata6603, the instruction placed at the reset vector must be a jmp ? absolute jump ? instruction to the reset handling routine. for the ata6602, the instruc- tion placed at the reset vector must be an rjmp ? relative jump ? instruction to the reset handling routine. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa (ata6602/ata6603 only ). the circuit diagram in figure 4-15 on page 67 shows the reset logic. table 4-20 on page 68 defines the electrical parameters of the reset circuitry. the i/o ports of the avr are immediately reset to their initial state when a reset source goes active. this does not require any clock source to be running. after all reset sources have gone inactive, a delay counter is invoked, stretching the internal reset. this allows the power to reach a stable level before normal operation starts. the time-out period of the delay counter is defined by the user through the sut and cksel fuses. the dif- ferent selections for the delay period are presented in ?clock sources? on page 50 . 67 4921e?auto?09/09 ata6602/ata6603 4.8.2 reset sources the ata6602/ata6603 has four sources of reset: ? power-on reset. the mcu is reset when the supply voltage is below the power-on reset threshold (v pot ). ? external reset. the mcu is reset when a low level is present on the reset pin for longer than the minimum pulse length. ? watchdog system reset. the mcu is reset when the watchdog timer period expires and the watchdog system reset mode is enabled. ? brown-out reset. the mcu is re set when the supply voltage v cc is below the brown-out reset threshold (v bot ) and the brown-out detector is enabled. figure 4-15. reset logic mcu status register (mcusr) brown-out reset circuit bodlevel [2..0] delay counters cksel[3:0] ck timeout wdrf borf extrf porf data bus clock generator spike filter pull-up resistor watchdog oscillator sut[1:0] power-on reset circuit rstdisbl watchdog timer reset circuit counter reset internal reset vcc s r q reset 68 4921e?auto?09/09 ata6602/ata6603 4.8.3 power-on reset a power-on reset (por) pulse is generated by an on-chip detection circuit. the detection level is defined in table 4-20 . the por is activated whenever v cc is below the detection level. the por circuit can be used to trigger the start-up reset, as well as to detect a failure in supply voltage. a power-on reset (por) circuit ensures that the device is reset from power-on. reaching the power-on reset threshold voltage invokes the delay counter, which determines how long the device is kept in reset after v cc rise. the reset signal is acti vated again, without any delay, when v cc decreases below the detection level. figure 4-16. mcu start-up, reset tied to v cc figure 4-17. mcu start-up, reset extended externally reset time-out internal reset t tout v rst v porma x v cc ccrr v v pormin reset time-out internal reset t tout v rst v cc table 4-20. power-on reset characteristics symbol parameter condition min typ max units v pot power-on reset threshold voltage (rising) 1.0 1.4 v power-on reset threshold voltage (falling) (1) 0.9 1.3 v v pormax vcc max. start voltage to ensure internal power-on reset signal 0.4 v v pormin vcc min. start voltage to ensure internal power-on reset signal -0.1 v v ccrr vcc rise rate to ensure power-on reset 0.01 v/ms v rst reset pin threshold voltage 0.1 v cc 0.9 v cc v note: 1. before rising, the supply has to be between v pormin and v pormax to ensure a reset. 69 4921e?auto?09/09 ata6602/ata6603 4.8.4 external reset an external reset is generated by a low level on the reset pin. reset pulses longer than the minimum pulse width (see table 4-20 on page 68 ) will generate a reset, ev en if the clock is not running. shorter pulses are not guaranteed to generate a reset. when the applied signal reaches the reset threshold voltage ? v rst ? on its positive edge, the delay counter starts the mcu after the time-out period ? t tout ? has expired. the external reset can be disabled by the rstdisbl fuse, see table 4-117 on page 300 . figure 4-18. external reset during operation 4.8.5 brown-out detection ata6602/ata6603 has an on-chip brown-out detection (bod) circuit for monitoring the v cc level during operation by comparing it to a fixed trigger level. the trigger level for the bod can be selected by the bodlevel fu ses. the trigger level has a hy steresis to ensure spike free brown-out detection. the hysteresis on the detection level should be interpreted as v bot+ = v bot + v hyst /2 and v bot- = v bot - v hyst /2. notes: 1. v bot may be below nominal minimum operating voltage for some devices. for devices where this is the case, the device is tested down to v cc = v bot during the production test. this guar- antees that a brown-out reset will occur before v cc drops to a voltage where correct operation of the microcontroller is no long er guaranteed. the test is performed using bodlevel = 110 and bodlevel = 101 for ata6602v/ata6603v, and bodlevel = 101 and bodlevel = 101 for ata6602/ata6603 . v cc reset time-out internal reset t tout v rst table 4-21. bodlevel fuse coding (1) bodlevel 2..0 fuses min v bot typ v bot max v bot units 111 bod disabled 110 1.8 v 101 2.7 100 4.3 011 reserved 010 001 000 70 4921e?auto?09/09 ata6602/ata6603 when the bod is enabled, and v cc decreases to a value below the trigger level (v bot- in figure 4-19 ), the brown-out reset is immediately activated. when v cc increases above the trigger level (v bot+ in figure 4-19 ), the delay counter starts the mcu after the time-out period t tout has expired. the bod circuit will only detect a drop in v cc if the voltage stays below the trigger level for lon- ger than t bod given in table 4-20 on page 68 . figure 4-19. brown-out reset during operation 4.8.6 watchdog system reset when the watchdog times out, it will generate a short reset pulse of one ck cycle duration. on the falling edge of this pulse, the delay timer starts counting the time-out period t tout . refer to ?watchdog timer? on page 72 for details on operation of the watchdog timer. figure 4-20. watchdog system reset during operation table 4-22. brown-out characteristics symbol parameter min typ max units v hyst brown-out detector hysteresis 50 mv t bod min pulse width on brown-out reset ns v cc reset time-out internal reset v bot - v bot+ t tout v cc reset 1 ck cycle t tout wdt time-out reset time-out internal reset 71 4921e?auto?09/09 ata6602/ata6603 4.8.7 mcu status register ? mcusr the mcu status register provides information on which reset source caused an mcu reset. ? bit 7..4: res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bit 3 ? wdrf: watchdog system reset flag this bit is set if a watchdog system reset occurs. the bit is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 2 ? borf: brown-out reset flag this bit is set if a brown-out reset occurs. the bit is reset by a power-on reset, or by writ- ing a logic zero to the flag. ? bit 1 ? extrf: external reset flag this bit is set if an external reset occurs. the bi t is reset by a power-on reset, or by writing a logic zero to the flag. ? bit 0 ? porf: power-on reset flag this bit is set if a power-on reset occurs. the bi t is reset only by writ ing a logic zero to the flag. to make use of the reset flags to identify a reset condition, the user should read and then reset the mcusr as early as possible in the program. if the register is cleared before another reset occurs, the source of the reset can be found by examining the reset flags. 4.8.8 internal voltage reference ata6602/ata6603 features an internal bandgap reference. this reference is used for brown-out detection, and it can be used as an input to the analog comparator or the adc. 4.8.8.1 voltage reference enable signals and start-up time the voltage reference has a start-up time that may influence the way it should be used. the start-up time is given in table 4-23 on page 72 . to save power, the reference is not always turned on. the reference is on during the following situations: 1. when the bod is enabled (by prog ramming the bodlevel [2..0] fuses). 2. when the bandgap reference is connected to the analog comparator (by setting the acbg bit in acsr). 3. when the adc is enabled. thus, when the bod is not enabled, after setting the acbg bit or enabling the adc, the user must always allow the reference to start up before the output from the analog comparator or adc is used. to reduce power consumption in power-down mode, the user can avoid the three conditions above to ensure that the reference is turned off before entering power-down mode. bit 76543210 ? ? ? ? wdrf borf extrf porf mcusr read/write r r r r r/w r/w r/w r/w initial value 0 0 0 0 see bit description 72 4921e?auto?09/09 ata6602/ata6603 note: 1. values are guidelines only. actual values are tbd. 4.8.9 watchdog timer ata6602/ata6603 has an enhanced watchdog timer (wdt). the main features are: ? clocked from separate on-chip oscillator ? 3 operating modes ? interrupt ? system reset ? interrupt and system reset ? selectable time-out period from 16 ms to 8s ? possible hardware fuse watchdog always on (wdton) for fail-safe mode figure 4-21. watchdog timer the watchdog timer (wdt) is a timer counting cycles of a separa te on-chip 128 khz oscillator. the wdt gives an interrupt or a system reset when the counter reaches a given time-out value. in normal operation mode, it is required that the system uses the wdr - watchdog timer reset - instruction to restart the counter before the ti me-out value is reached. if the system doesn't restart the counter, an interrupt or system reset will be issued. table 4-23. internal voltage refe rence characteristics (1) symbol parameter condition min typ max units v bg bandgap reference voltage tbd 1.0 1.1 1.2 v t bg bandgap reference start-up time tbd 40 70 s i bg bandgap reference current consumption tbd 10 tbd a 128khz oscillator osc/2k osc/4k osc/8k osc/16k osc/32k osc/64k osc/128k osc/256k osc/512k osc/1024k wdp0 wdp1 wdp2 wdp3 watchdog reset wde wdif wdie mcu reset interrupt watchog prescaler 73 4921e?auto?09/09 ata6602/ata6603 in interrupt mode, the wdt gives an interrupt when the timer expires. this interrupt can be used to wake the device from sleep-modes, and also as a general system timer. one example is to limit the maximum time allowed for certain operations, giving an interrupt when the operation has run longer than expected. in system reset mode, the wdt gives a reset when the timer expires. this is typically used to prevent sys tem hang-up in case of runaway code. the third mode, interrupt and system reset mode, combines the other two modes by first giving an inter- rupt and then switch to system reset mode. this mode will for instance allow a safe shutdown by saving critical parameters before a system reset. the watchdog always on (wdton ) fuse, if programmed, will forc e the watchdog timer to sys- tem reset mode. with the fuse programmed the system reset mode bit (wde) and interrupt mode bit (wdie) are locked to 1 and 0 respectively. to further ensure program security, altera- tions to the watchdog set-up must follow timed sequences. the sequence for clearing wde and changing time-out configuration is as follows: 1. in the same operation, write a logic one to the watchdog change enable bit (wdce) and wde. a logic one must be written to wde regardless of the previous value of the wde bit. 2. within the next four clock cycles, write the wde and watchdog prescaler bits (wdp) as desired, but with the wdce bit cleared. this must be done in one operation. the following code example shows one assembly and one c function for turning off the watch- dog timer. the example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during th e execution of these functions. 74 4921e?auto?09/09 ata6602/ata6603 note: 1. the example code assumes that the pa rt specific header file is included. note: if the watchdog is accidentally enabled, for exam ple by a runaway pointer or brown-out condition, the device will be reset and the watchdog timer will stay enabled. if the code is not set up to han- dle the watchdog, this might lead to an eternal loop of time-out resets. to avoid this situation, the application software should always clear the watchdog system reset flag (wdrf) and the wde control bit in the initiali zation routine, even if the watchdog is not in use. assembly code example (1) wdt_off: ; turn off global interrupt cli ; reset watchdog timer wdr ; clear wdrf in mcusr in r16, mcusr andi r16, (0xff & (0< 77 4921e?auto?09/09 ata6602/ata6603 ? bit 5, 2..0 - wdp3..0: watchdog timer prescaler 3, 2, 1 and 0 the wdp3..0 bits determine the watchdog time r prescaling when the watchdog timer is running. the different prescaling values and their corresponding time-out periods are shown in table 4-25 . 4.9 interrupts this section describes the specifics of the interrupt handling as performed in ata6602/ata6603. for a general explanation of the avr interrupt handling, refer to ?reset and interrupt handling? on page 37 . the interrupt vectors in ata6602 and ata6603 are generally the same, with the following differences: ? each interrupt vector occupies two instruction words in ata6603, and one instruction word in ata6602. ? in ata6602 and ata6603, the reset vector is affected by the bootrst fuse, and the interrupt vector start address is affected by the ivsel bit in mcucr. table 4-25. watchdog timer prescale select wdp3 wdp2 wdp1 wdp0 number of wdt oscillator cycles typical time-out at v cc = 5.0v 0000 2k (2048) cycles 16 ms 0001 4k (4096) cycles 32 ms 0010 8k (8192) cycles 64 ms 0011 16k (16 384) cycles 0.125 s 0100 32k (32 768) cycles 0.25 s 0101 64k (65 536) cycles 0.5 s 0110 128k (13 1072) cycles 1.0 s 0111 256k (26 2144) cycles 2.0 s 1000 512k (52 4288) cycles 4.0 s 1001 1024k (10 48576) cycles 8.0 s 1010 reserved 1011 1100 1101 1110 1111 78 4921e?auto?09/09 ata6602/ata6603 4.9.1 interrupt vectors in ata6602 notes: 1. when the bootrst fuse is programmed, the device will jump to the boot loader address at reset (see ?boot loader support ? read-while-write self-programming, ata6602 and ata6603? on page 282 ). 2. when the ivsel bit in mcucr is set, interrupt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. table 4-27 on page 79 shows reset and interrupt vectors placement for the various combina- tions of bootrst and ivsel settings. if the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. table 4-26. reset and interrupt vectors in ata6602 vector no. program address (2) source interrup t definition 1 0x000 (1) reset external pin, power-on reset, brown- out reset and watchdog system reset 2 0x001 int0 external interrupt request 0 3 0x002 int1 external interrupt request 1 4 0x003 pcint0 pin change interrupt request 0 5 0x004 pcint1 pin change interrupt request 1 6 0x005 pcint2 pin change interrupt request 2 7 0x006 wdt watchdog time-out interrupt 8 0x007 timer2 compa timer/c ounter2 compare match a 9 0x008 timer2 compb timer/c ounter2 compare match b 10 0x009 timer2 ovf timer/counter2 overflow 11 0x00a timer1 capt timer/counter1 capture event 12 0x00b timer1 compa timer/counter1 compare match a 13 0x00c timer1 compb timer/c outner1 compare match b 14 0x00d timer1 ovf timer/counter1 overflow 15 0x00e timer0 compa timer/counter0 compare match a 16 0x00f timer0 compb timer/c ounter0 compare match b 17 0x010 timer0 ovf timer/counter0 overflow 18 0x011 spi, stc spi serial transfer complete 19 0x012 usart, rx usart rx complete 20 0x013 usart, udre usart, data register empty 21 0x014 usart, tx usart, tx complete 22 0x015 adc adc conversion complete 23 0x016 ee ready eeprom ready 24 0x017 analog comp analog comparator 25 0x018 twi 2-wire serial interface 26 0x019 spm ready store program memory ready 79 4921e?auto?09/09 ata6602/ata6603 note: 1. the boot reset address is shown in table 4-107 on page 296 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. the most typical and general program setup for the reset and interrupt vector addresses in ata6602 is: address labels code comments 0x000 rjmp reset ; reset handler 0x001 rjmp ext_int0 ; irq0 handler 0x002 rjmp ext_int1 ; irq1 handler 0x003 rjmp pcint0 ; pcint0 handler 0x004 rjmp pcint1 ; pcint1 handler 0x005 rjmp pcint2 ; pcint2 handler 0x006 rjmp wdt ; watchdog timer handler 0x007 rjmp tim2_compa ; timer2 compare a handler 0x008 rjmp tim2_compb ; timer2 compare b handler 0x009 rjmp tim2_ovf ; timer2 overflow handler 0x00a rjmp tim1_capt ; timer1 capture handler 0x00b rjmp tim1_compa ; timer1 compare a handler 0x00c rjmp tim1_compb ; timer1 compare b handler 0x00d rjmp tim1_ovf ; timer1 overflow handler 0x00e rjmp tim0_compa ; timer0 compare a handler 0x00f rjmp tim0_compb ; timer0 compare b handler 0x010 rjmp tim0_ovf ; timer0 overflow handler 0x011 rjmp spi_stc ; spi transfer complete handler 0x012 rjmp usart_rxc ; usart, rx complete handler 0x013 rjmp usart_udre ; usart, udr empty handler 0x014 rjmp usart_txc ; usart, tx complete handler 0x015 rjmp adc ; adc conversion complete handler 0x016 rjmp ee_rdy ; eeprom ready handler 0x017 rjmp ana_comp ; analog comparator handler 0x018 rjmp twi ; 2-wire serial interface handler 0x019 rjmp spm_rdy ; store program memory ready handler ; 0x01areset: ldi r16, high(ramend); main program start 0x01b out sph,r16 ; set stack pointer to top of ram 0x01c ldi r16, low(ramend) 0x01d out spl,r16 0x01e sei ; enable interrupts 0x01f 80 4921e?auto?09/09 ata6602/ata6603 when the bootrst fuse is unprogrammed, the boot section size set to 2k bytes and the ivsel bit in the mcucr register is set before an y interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in ata6602 is: address labels code comments 0x000 reset: ldi r16,high(ramend); main program start 0x001 out sph,r16 ; set stack pointer to top of ram 0x002 ldi r16,low(ramend) 0x003 out spl,r16 0x004 sei ; enable interrupts 0x005 81 4921e?auto?09/09 ata6602/ata6603 when the bootrst fuse is programmed, the boot section size set to 2k bytes and the ivsel bit in the mcucr register is set before any interr upts are enabled, the mo st typical and general program setup for the reset and interrupt vector addresses in ata6602 is: address labels code comments ; .org 0xc00 0xc00 rjmp reset ; reset handler 0xc01 rjmp ext_int0 ; irq0 handler 0xc02 rjmp ext_int1 ; irq1 handler ... ... ... ; 0xc19 rjmp spm_rdy ; store program memory ready handler ; 0xc1a reset: ldi r16,high(ramend); main program start 0xc1b out sph,r16 ; set stack pointer to top of ram 0xc1c ldi r16,low(ramend) 0xc1d out spl,r16 0xc1e sei ; enable interrupts 0xc1f 82 4921e?auto?09/09 ata6602/ata6603 notes: 1. when the bootrst fuse is programmed, the device will jump to the boot loader address at reset (see ?boot loader support ? read-while-write self-programming, ata6602 and ata6603? on page 282 ). 2. when the ivsel bit in mcucr is set, interrupt vectors will be moved to the start of the boot flash section. the address of each interrupt vector will then be the address in this table added to the start address of the boot flash section. table 4-29 shows reset and interrupt vectors plac ement for the various combinations of bootrst and ivsel settings. if the program never enables an in terrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. this is also the case if the reset vector is in the application section while the interrupt vectors are in the boot section or vice versa. note: 1. the boot reset address is shown in table 4-107 on page 296 . for the bootrst fuse ?1? means unprogrammed while ?0? means programmed. 22 0x002a adc adc conversion complete 23 0x002c ee ready eeprom ready 24 0x002e analog comp analog comparator 25 0x0030 twi 2-wire serial interface 26 0x0032 spm ready store program memory ready table 4-28. reset and interrupt vectors in ata6603 (continued) vector no. program address (2) source interrup t definition table 4-29. reset and interrupt vectors placement in ata6603 (1) bootrst ivsel reset address interrupt vectors start address 1 0 0x000 0x001 1 1 0x000 boot reset address + 0x0002 0 0 boot reset address 0x001 0 1 boot reset address boot reset address + 0x0002 83 4921e?auto?09/09 ata6602/ata6603 the most typical and general program setup for the reset and interrupt vector addresses in ata6603 is: address labels code comments 0x0000 jmp reset ; reset handler 0x0002 jmp ext_int0 ; irq0 handler 0x0004 jmp ext_int1 ; irq1 handler 0x0006 jmp pcint0 ; pcint0 handler 0x0008 jmp pcint1 ; pcint1 handler 0x000a jmp pcint2 ; pcint2 handler 0x000c jmp wdt ; watchdog timer handler 0x000e jmp tim2_compa ; timer2 compare a handler 0x0010 jmp tim2_compb ; timer2 compare b handler 0x0012 jmp tim2_ovf ; timer2 overflow handler 0x0014 jmp tim1_capt ; timer1 capture handler 0x0016 jmp tim1_compa ; timer1 compare a handler 0x0018 jmp tim1_compb ; timer1 compare b handler 0x001a jmp tim1_ovf ; timer1 overflow handler 0x001c jmp tim0_compa ; timer0 compare a handler 0x001e jmp tim0_compb ; timer0 compare b handler 0x0020 jmp tim0_ovf ; timer0 overflow handler 0x0022 jmp spi_stc ; spi transfer complete handler 0x0024 jmp usart_rxc ; usart, rx complete handler 0x0026 jmp usart_udre ; usart, udr empty handler 0x0028 jmp usart_txc ; usart, tx complete handler 0x002a jmp adc ; adc conversion complete handler 0x002c jmp ee_rdy ; eeprom ready handler 0x002e jmp ana_comp ; analog comparator handler 0x0030 jmp twi ; 2-wire serial interface handler 0x0032 jmp spm_rdy ; store program memory ready handler ; 0x0033reset: ldi r16, high(ramend); main program start 0x0034 out sph,r16 ; set stack pointer to top of ram 0x0035 ldi r16, low(ramend) 0x0036 out spl,r16 0x0037 sei ; enable interrupts 0x0038 84 4921e?auto?09/09 ata6602/ata6603 when the bootrst fuse is unprogrammed, the boot section size set to 2k bytes and the ivsel bit in the mcucr register is set before an y interrupts are enabled, the most typical and general program setup for the reset and interrupt vector addresses in ata6603 is: address labels code comments 0x0000 reset: ldi r16,high(ramend); main program start 0x0001 out sph,r16 ; set stack pointer to top of ram 0x0002 ldi r16,low(ramend) 0x0003 out spl,r16 0x0004 sei ; enable interrupts 0x0005 85 4921e?auto?09/09 ata6602/ata6603 when the bootrst fuse is programmed, the boot section size set to 2k bytes and the ivsel bit in the mcucr register is set before any interr upts are enabled, the mo st typical and general program setup for the reset and interrupt vector addresses in ata6603 is: address labels code comments ; .org 0x1c00 0x1c00 jmp reset ; reset handler 0x1c02 jmp ext_int0 ; irq0 handler 0x1c04 jmp ext_int1 ; irq1 handler ... ... ... ; 0x1c32 jmp spm_rdy ; store program memory ready handler ; 0x1c33 reset: ldi r16,high(ramend); main program start 0x1c34 out sph,r16 ; set stack pointer to top of ram 0x1c35 ldi r16,low(ramend) 0x1c36 out spl,r16 0x1c37 sei ; enable interrupts 0x1c38 86 4921e?auto?09/09 ata6602/ata6603 ? bit 0 ? ivce: interrupt vector change enable the ivce bit must be written to logic one to enable change of the ivsel bit. ivce is cleared by hardware four cycles after it is written or when ivsel is written. setting the ivce bit will disable interrupts, as explained in the ivsel description ab ove. see code example below. 4.10 i/o-ports 4.10.1 introduction all avr ports have true read-modi fy-write functionality when used as general digital i/o ports. this means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with the sbi and cbi instructions. the same applies when chang- ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as input). each output buffer has symmetrical drive characteristics with both high sink and source capability. the pin driver is stro ng enough to drive led displays directly. all port pins have indi- vidually selectable pull-up resistors with a suppl y-voltage invariant resistance. all i/o pins have protection diodes to both v cc and ground as indicated in figure 4-22 on page 87 . refer to ?electrical characteristics? on page 318 for a complete list of parameters. assembly code example move_interrupts: ; enable change of interrupt vectors ldi r16, (1< 88 4921e?auto?09/09 ata6602/ata6603 4.10.2 ports as general digital i/o the ports are bi-directional i/o ports with optional internal pull-ups. figure 4-23 shows a func- tional description of one i/o-port pin, here generically called pxn. figure 4-23. general digital i/o (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. 4.10.2.1 configuring the pin each port pin consists of three register bits: ddxn, portxn, and pinxn. as shown in ?register description for i/o ports? on page 105 , the ddxn bits are accessed at the ddrx i/o address, the portxn bits at the portx i/o address, and the pinxn bits at the pinx i/o address. the ddxn bit in the ddrx register selects the direct ion of this pin. if ddxn is written logic one, pxn is configured as an output pin. if ddxn is written logic zero, pxn is configured as an input pin. if portxn is written logic one when the pin is c onfigured as an input pin, the pull-up resistor is activated. to switch the pull-up resistor off, portxn has to be written logic zero or the pin has to be configured as an output pin. the port pins are tri-stated when reset condition becomes active, even if no clocks are running. if portxn is written logic one when the pin is conf igured as an output pin, the port pin is driven high (one). if portxn is written logic zero when the pin is configured as an output pin, the port pin is driven low (zero). clk rpx rrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q reset reset q q d q clr q d portxn q clr q d ddxn pinxn data b u s sleep sleep: sleep control pxn i/o wpx 0 1 wrx wpx: write pinx register 89 4921e?auto?09/09 ata6602/ata6603 4.10.2.2 toggling the pin writing a logic one to pinxn toggles the value of portxn, independent on the value of ddrxn. note that the sbi instruction can be used to toggle one single bit in a port. 4.10.2.3 switching between input and output when switching between tri-state ({ddxn, portxn} = 0b00) and output high ({ddxn, portxn} = 0b11), an intermediate state with either pull-up enabled {ddxn, portxn} = 0b01) or output low ({ddxn, portxn} = 0b10) must occur. norma lly, the pull-up enabled state is fully accept- able, as a high-impedant enviro nment will not notice the differenc e between a strong high driver and a pull-up. if this is not the case, the pud bit in the mcucr register can be set to disable all pull-ups in all ports. switching between input with pull-up and output low generates the same problem. the user must use either the tri-state ({ddxn, portxn} = 0b00) or the output high state ({ddxn, portxn} = 0b11) as an intermediate step. table 4-30 summarizes the control signals for the pin value. 4.10.2.4 reading the pin value independent of the setting of data direction bit ddxn, the port pin can be read through the pinxn register bit. as shown in figure 4-23 on page 88 , the pinxn register bit and the preced- ing latch constitute a synchronizer. this is needed to avoid metastability if the physical pin changes value near the edge of the internal clock, but it also introduces a delay. figure 4-24 on page 90 shows a timing diagram of the synchroni zation when reading an externally applied pin value. the maximum and minimum propagation delays are denoted t pd,max and t pd,min respectively. table 4-30. port pin configurations ddxn portxn pud (in mcucr) i/o pull-up comment 0 0 x input no tri-state (hi-z) 0 1 0 input yes pxn will source current if ext. pulled low. 0 1 1 input no tri-state (hi-z) 1 0 x output no output low (sink) 1 1 x output no output high (source) 90 4921e?auto?09/09 ata6602/ata6603 figure 4-24. synchronization when reading an externally applied pin value consider the clock period starting shortly after the first falling edge of the system cl ock. the latch is closed when the clock is low, and goes transpa rent when the clock is high, as indicated by the shaded region of the ?sync latch? signal. the signal value is latched when the system clock goes low. it is clocked into the pinxn register at the succeeding positive clock edge. as indi- cated by the two arrows tpd,max and tpd,min, a single signal tr ansition on the pin will be delayed between ? and 1? system clock period depending upon the time of assertion. when reading back a software assigned pin value, a nop instruction must be inserted as indi- cated in figure 4-25 . the out instruction sets the ?sync latch? signal at the positive edge of the clock. in this case, the delay tpd through the synchronizer is 1 system clock period. figure 4-25. synchronization when reading a software assigned pin value xxx in r17, pinx 0x00 0xff instructions sync latch pinxn r17 xxx system clk t pd, max t pd, min out portx, r16 nop in r17, pinx 0xff 0x00 0xff system clk r16 instructions sync latch pinxn r17 t pd 91 4921e?auto?09/09 ata6602/ata6603 the following code example shows how to set port b pins 0 and 1 high, 2 and 3 low, and define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. the resulting pin values are read back again, but as previously di scussed, a nop instruction is included to be able to read back the value recently assigned to some of the pins. note: 1. for the assembly program, two temporary registers are used to minimize the time from pull-ups are set on pins 0, 1, 6, and 7, until the di rection bits are correctly set, defining bit 2 and 3 as low and redefining bits 0 and 1 as strong high drivers. assembly code example (1) ... ; define pull-ups and set outputs high ; define directions for port pins ldi r16,(1< 93 4921e?auto?09/09 ata6602/ata6603 4.10.3 alternate port functions most port pins have alternate functions in addition to being general digital i/os. figure 4-26 shows how the port pin control signals from the simplified figure 4-23 on page 88 can be over- ridden by alternate functions. the overriding sign als may not be present in all port pins, but the figure serves as a generic description applicable to all port pins in the avr microcontroller family. figure 4-26. alternate port functions (1) note: 1. wrx, wpx, wdx, rrx, rpx, and rdx are common to all pins within the same port. clk i/o , sleep, and pud are common to all ports. all other signals are unique for each pin. clk rpx rrx wrx rdx wdx pud synchronizer wdx: write ddrx wrx: write portx rrx: read portx register rpx: read portx pin pud: pullup disable clk i/o : i/o clock rdx: read ddrx d l q q set clr 0 1 0 1 0 1 dixn aioxn dieoexn pvovxn pvoexn ddovxn ddoexn puoexn puovxn puoexn: pxn pull-up override enable puovxn: pxn pull-up override value ddoexn: pxn data direction override enable ddovxn: pxn data direction override value pvoexn: pxn port value override enable pvovxn: pxn port value override value dixn: digital input pin n on portx aioxn: analog input/output pin n on portx reset reset q q d clr q q d clr q q d clr pinxn portxn ddxn data bus 0 1 dieovxn sleep dieoexn: pxn digital input-enable override enable dieovxn: pxn digital input-enable override value sleep: sleep control pxn i/o 0 1 ptoexn ptoexn: pxn, port toggle override enable wpx: write pinx wpx 94 4921e?auto?09/09 ata6602/ata6603 table 4-31 summarizes the function of the overriding signals. the pin and port indexes from fig- ure 4-26 on page 93 are not shown in the succeeding tables. the overriding signals are generated internally in the modules having the alternate function. the following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. refer to the alternate function description for further details. table 4-31. generic description of overriding signals for alternate functions signal name full name description puoe pull-up override enable if this signal is set, the pull- up enable is controlled by the puov signal. if this signal is cleared, the pull-up is enabled when {ddxn, portxn, pud} = 0b010. puov pull-up override value if puoe is set, the pull-up is enabled/disabled when puov is set/cleared, regardless of the setting of the ddxn, portxn, and pud register bits. ddoe data direction override enable if this signal is set, the output driver enable is controlled by the ddov signal. if this signal is cleared, the output driver is enabled by the ddxn register bit. ddov data direction override value if ddoe is set, the output dr iver is enabled/disabled when ddov is set/cleared, regardle ss of the setting of the ddxn register bit. pvoe port value override enable if this signal is set and the output driver is enabled, the port value is controlled by the pvov signal. if pvoe is cleared, and the output driver is enabled, the port value is controlled by the portxn register bit. pvov port value override value if pvoe is set, the port value is set to pvov, regardless of the setting of the portxn register bit. ptoe port toggle override enable if ptoe is set, the portxn register bit is inverted. dieoe digital input enable override enable if this bit is set, the digital in put enable is controlled by the dieov signal. if this signal is cleared, the digital input enable is determined by mcu state (normal mode, sleep mode). dieov digital input enable override value if dieoe is set, the digital input is enabled/disabled when dieov is set/cleared, regardless of the mcu state (normal mode, sleep mode). di digital input this is the digital input to altern ate functions. in the figure, the signal is connected to the output of the schmitt trigger but before the synchronizer. unless the digital input is used as a clock source, the module with the alternate function will use its own synchronizer. aio analog input/output this is the analog input/output to/from alternate functions. the signal is connected directly to the pad, and can be used bi-directionally. 95 4921e?auto?09/09 ata6602/ata6603 4.10.3.1 mcu control register ? mcucr ? bit 4 ? pud: pull-up disable when this bit is written to one, the pull-ups in the i/o ports are disabled even if the ddxn and portxn registers are configured to enable the pull-ups ({ddxn, portxn} = 0b01). see ?configuring the pin? on page 88 for more details about this feature. 4.10.3.2 alternate functions of port b the port b pins with alternate functions are shown in table 4-32 . bit 7 6 5 4 3 2 1 0 ? ? ?pud ? ? ivsel ivce mcucr read/write r r r r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 4-32. port b pins alternate functions port pin alternate functions pb7 xtal2 ( chip clock oscillator pin 2 ) tosc2 ( timer oscillator pin 2 ) pcint7 (pin change interrupt 7) pb6 xtal1 ( chip clock oscillator pin 1 or external clock input ) tosc1 ( timer oscillator pin 1 ) pcint6 (pin change interrupt 6) pb5 sck (spi bus master clock input) pcint5 (pin change interrupt 5) pb4 miso (spi bus master input/slave output) pcint4 (pin change interrupt 4) pb3 mosi (spi bus master output/slave input) oc2a (timer/counter2 output compare match a output) pcint3 (pin change interrupt 3) pb2 ss (spi bus master slave select) oc1b (timer/counter1 output compare match b output) pcint2 (pin change interrupt 2) pb1 oc1a (timer/counter1 output compare match a output) pcint1 (pin change interrupt 1) pb0 icp1 (timer/counter1 input capture input) clko (divided system clock output) pcint0 (pin change interrupt 0) 96 4921e?auto?09/09 ata6602/ata6603 the alternate pin configuration is as follows: ? xtal2/tosc2/pcint7 ? port b, bit 7 xtal2: chip clock oscillator pin 2. used as cl ock pin for crystal osc illator or low-frequency crystal oscillator. when used as a clock pi n, the pin can not be used as an i/o pin. tosc2: timer oscillator pin 2. used only if internal calibrated rc oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in assr. when the as2 bit in assr is set (one) and the exclk bit is cleared (z ero) to enable asyn- chronous clocking of timer/co unter2 using the crystal oscilla tor, pin pb7 is disconnected from the port, and becomes the inverting output of the oscillator amplifier. in this mode, a crystal oscillator is connected to this pin, and the pin ca nnot be used as an i/o pin. pcint7: pin change interrupt source 7. the pb7 pin can serve as an external interrupt source. if pb7 is used as a clock pin, ddb 7, portb7 and pinb7 will all read 0. ? xtal1/tosc1/pcint6 ? port b, bit 6 xtal1: chip clock oscillator pin 1. used for all chip clock sources except internal calibrated rc oscillator. when used as a clock pin, the pin can not be used as an i/o pin. tosc1: timer oscillator pin 1. used only if internal calibrated rc oscillator is selected as chip clock source, and the asynchronous timer is enabled by the correct setting in assr. when the as2 bit in assr is set (one) to enabl e asynchronous clocking of timer/counter2, pin pb6 is disconnected from the port, and be comes the input of th e inverting oscillator amplifier. in this mode, a crystal oscillator is connected to this pin, and the pin can not be used as an i/o pin. pcint6: pin change interrupt source 6. the pb6 pin can serve as an external interrupt source. if pb6 is used as a clock pin, ddb 6, portb6 and pinb6 will all read 0. ? sck/pcint5 ? port b, bit 5 sck: master clock output, slave clock input pin for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb5. when the spi is enabled as a master, the data direction of this pin is controlled by ddb5. when the pin is forced by the spi to be an input, the pull-up can still be contro lled by the portb5 bit. pcint5: pin change interrupt source 5. the pb5 pin can serve as an external interrupt source. ? miso/pcint4 ? port b, bit 4 miso: master data input, slave data output pin for spi channel. when the spi is enabled as a master, this pin is configured as an input regardless of the setting of ddb4. when the spi is enabled as a slave, the data direction of this pin is controlled by ddb4. when the pin is forced by the spi to be an input, the pull-up ca n still be controlled by the portb4 bit. pcint4: pin change interrupt source 4. the pb4 pin can serve as an external interrupt source. 97 4921e?auto?09/09 ata6602/ata6603 ? mosi/oc2/pcint3 ? port b, bit 3 mosi: spi master data output, slave data i nput for spi channel. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb3. when the spi is enabled as a master, the data direction of this pin is controlled by ddb3. when the pin is forced by the spi to be an input, the pull-up can still be contro lled by the portb3 bit. oc2, output compare match output: the pb3 pin can serve as an external output for the timer/counter2 compare match. the pb3 pin has to be configured as an output (ddb3 set (one)) to serve this function. the oc2 pin is also the output pin for the pwm mode timer function. pcint3: pin change interrupt source 3. the pb3 pin can serve as an external interrupt source. ? ss/oc1b/pcint2 ? port b, bit 2 ss : slave select input. when the spi is enabled as a slave, this pin is configured as an input regardless of the setting of ddb2. as a slave, the spi is activated when this pin is driven low. when the spi is enabled as a master , the data direction of this pin is controlled by ddb2. when the pin is forced by the spi to be an input, t he pull-up can still be controlled by the portb2 bit. oc1b, output compare match output: the pb2 pin can serve as an external output for the timer/counter1 compare match b. the pb2 pin has to be configured as an output (ddb2 set (one)) to serve this function. the oc1b pin is also the output pin for the pwm mode timer function. pcint2: pin change interrupt source 2. the pb2 pin can serve as an external interrupt source. ? oc1a/pcint1 ? port b, bit 1 oc1a, output compare match output: the pb1 pin can serve as an external output for the timer/counter1 compare match a. the pb1 pin has to be configured as an output (ddb1 set (one)) to serve this function. the oc1a pin is also the output pin for the pwm mode timer function. pcint1: pin change interrupt source 1. the pb1 pin can serve as an external interrupt source. ? icp1/clko/pcint0 ? port b, bit 0 icp1, input capture pin: the pb0 pin can act as an input capture pin for timer/counter1. clko, divided system clock: the divided system clock can be output on the pb0 pin. the divided system clock w ill be output if the ckout fuse is programmed, regardless of the portb0 and ddb0 settings. it will also be output during reset. pcint0: pin change interrupt source 0. the pb0 pin can serve as an external interrupt source. table 4-33 on page 98 and table 4-34 on page 98 relate the alternate functions of port b to the overriding signals shown in figure 4-26 on page 93 . spi mstr input and spi slave output constitute the miso signal, while mo si is divided into spi mstr output and spi slave input. 98 4921e?auto?09/09 ata6602/ata6603 notes: 1. intrc means that one of the internal rc oscillators ar e selected (by the cksel fuses), extck means that external clock is selected (by the cksel fuses). table 4-33. overriding signals for alternate functions in pb7..pb4 signal name pb7/xtal2/ tosc2/pcint7 (1) pb6/xtal1/ tosc1/pcint6 (1) pb5/sck/ pcint5 pb4/miso/ pcint4 puoe intrc ? extck + as2 intrc + as2 spe ? mstr spe ? mstr puov 0 0 portb5 ? pud portb4 ? pud ddoe intrc ? extck + as2 intrc + as2 spe ? mstr spe ? mstr ddov0000 pvoe 0 0 spe ? mstr spe ? mstr pvov 0 0 sck output spi slave output dieoe intrc ? extck + as2 + pcint7 ? pcie0 intrc + as2 + pcint6 ? pcie0 pcint5 ? pcie0 pcint4 ? pcie0 dieov (intrc + extck) ? as2 intrc ? as2 11 di pcint7 input pcint6 input pcint5 input sck input pcint4 input spi mstr input aio oscillator output oscillator/clock input ?? table 4-34. overriding signals for alternate functions in pb3..pb0 signal name pb3/mosi/ oc2/pcint3 pb2/ss / oc1b/pcint2 pb1/oc1a/ pcint1 pb0/icp1/ pcint0 puoe spe ? mstr spe ? mstr 00 puov portb3 ? pud portb2 ? pud 00 ddoe spe ? mstr spe ? mstr 00 ddov0000 pvoe spe ? mstr + oc2a enable oc1b enable oc1a enable 0 pvov spi mstr output + oc2a oc1b oc1a 0 dieoe pcint3 ? pcie0 pcint2 ? pcie 0 pcint1 ? pcie0 pcint0 ? pcie0 dieov1111 di pcint3 input spi slave input pcint2 input spi ss pcint1 input pcint0 input icp1 input aio???? 99 4921e?auto?09/09 ata6602/ata6603 4.10.3.3 alternate functions of port c the port c pins with alternate functions are shown in table 4-35 . the alternate pin configuration is as follows: ? reset /pcint14 ? port c, bit 6 reset , reset pin: when the rstdisbl fuse is programmed, this pin functions as a nor- mal i/o pin, and the part will have to rely on power-on rese t and brown-out reset as its reset sources. when the rstdisbl fuse is unprogrammed, the reset circuitry is connected to the pin, and the pin can not be used as an i/o pin. if pc6 is used as a reset pin, ddc6, portc6 and pinc6 will all read 0. pcint14: pin change interrupt source 14. the pc6 pin can serve as an external interrupt source. ? scl/adc5/pcint13 ? port c, bit 5 scl, 2-wire serial interface clock: when the twen bit in twcr is set (one) to enable the 2-wire serial interface, pin pc5 is disconnected from the port and becomes the serial clock i/o pin for the 2-wire serial interface. in this mode, there is a spike filter on the pin to sup- press spikes shorter than 50 ns on the input si gnal, and the pin is driven by an open drain driver with slew-rate limitation. pc5 can also be used as adc input channel 5. note that adc input channel 5 uses digital power. pcint13: pin change interrupt source 13. the pc5 pin can serve as an external interrupt source. table 4-35. port c pins alternate functions port pin alternate function pc6 reset (reset pin) pcint14 (pin change interrupt 14) pc5 adc5 (adc input channel 5) scl (2-wire serial bus clock line) pcint13 (pin change interrupt 13) pc4 adc4 (adc input channel 4) sda (2-wire serial bus data input/output line) pcint12 (pin change interrupt 12) pc3 adc3 (adc input channel 3) pcint11 (pin change interrupt 11) pc2 adc2 (adc input channel 2) pcint10 (pin change interrupt 10) pc1 adc1 (adc input channel 1) pcint9 (pin change interrupt 9) pc0 adc0 (adc input channel 0) pcint8 (pin change interrupt 8) 100 4921e?auto?09/09 ata6602/ata6603 ? sda/adc4/pcint12 ? port c, bit 4 sda, 2-wire serial interface data: when the twen bit in twcr is set (one) to enable the 2-wire serial interface, pin pc4 is disconnec ted from the port and becomes the serial data i/o pin for the 2-wire serial interface. in this mode, there is a spike filter on the pin to sup- press spikes shorter than 50 ns on the input si gnal, and the pin is driven by an open drain driver with slew-rate limitation. pc4 can also be used as adc input channel 4. note that adc input channel 4 uses digital power. pcint12: pin change interrupt source 12. the pc4 pin can serve as an external interrupt source. ? adc3/pcint11 ? port c, bit 3 pc3 can also be used as adc input channel 3. note that adc input channel 3 uses analog power. pcint11: pin change interrupt source 11. the pc3 pin can serve as an external interrupt source. ? adc2/pcint10 ? port c, bit 2 pc2 can also be used as adc input channel 2. note that adc input channel 2 uses analog power. pcint10: pin change interrupt source 10. the pc2 pin can serve as an external interrupt source. ? adc1/pcint9 ? port c, bit 1 pc1 can also be used as adc input channel 1. note that adc input channel 1 uses analog power. pcint9: pin change interrupt source 9. the pc1 pin can serve as an external interrupt source. ? adc0/pcint8 ? port c, bit 0 pc0 can also be used as adc input channel 0. note that adc input channel 0 uses analog power. pcint8: pin change interrupt source 8. the pc0 pin can serve as an external interrupt source. 101 4921e?auto?09/09 ata6602/ata6603 table 4-36 and table 4-37 relate the alternate functions of port c to the overriding signals shown in figure 4-26 on page 93 . note: 1. when enabled, the 2-wire serial interface enables slew-rate controls on the output pins pc4 and pc5. this is not shown in the figure. in addition, spike filters are connected between the aio outputs shown in the port figure and the digital logic of the twi module. table 4-36. overriding signals for alternate functions in pc6..pc4 (1) signal name pc6/reset /pcint14 pc5/scl/adc5/pcint13 pc4/sda/adc4/pcint12 puoe rstdisbl twen twen puov 1 portc5 ? pud portc4 ? pud ddoe rstdisbl twen twen ddov 0 scl_out sda_out pvoe 0 twen twen pvov 0 0 0 dieoe rstdisbl + pcint14 ? pcie1 pcint13 ? pcie1 + adc5d pcint12 ? pcie1 + adc4d dieov rstdisbl pcint13 ? pcie1 pcint12 ? pcie1 di pcint14 input pcint13 input pcint12 input aio reset input adc5 input / scl input adc4 input / sda input table 4-37. overriding signals for alternate functions in pc3..pc0 signal name pc3/adc3/ pcint11 pc2/adc2/ pcint10 pc1/adc1/ pcint9 pc0/adc0/ pcint8 puoe0000 puov0000 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe0000 pvov0000 dieoe pcint11 ? pcie1 + adc3d pcint10 ? pcie1 + adc2d pcint9 ? pcie1 + adc1d pcint8 ? pcie1 + adc0d dieov pcint11 ? pcie1 pcint10 ? pc ie1 pcint9 ? pcie1 pcint8 ? pcie1 di pcint11 input pcint10 input pcint9 input pcint8 input aio adc3 input adc2 input adc1 input adc0 input 102 4921e?auto?09/09 ata6602/ata6603 4.10.3.4 alternate functions of port d the port d pins with alternate functions are shown in table 4-38 . the alternate pin configuration is as follows: ? ain1/oc2b/pcint23 ? port d, bit 7 ain1, analog comparator negative input. confi gure the port pin as input with the internal pull-up switched off to avoid the digital port functi on from interfering with the function of the analog comparator. pcint23: pin change interrupt source 23. the pd7 pin can serve as an external interrupt source. ? ain0/oc0a/pcint22 ? port d, bit 6 ain0, analog comparator positive input. configure the port pin as input with the internal pull-up switched off to avoid the digital port functi on from interfering with the function of the analog comparator. oc0a, output compare match output: the pd6 pin can serve as an external output for the timer/counter0 compare match a. the pd6 pin has to be configured as an output (ddd6 set (one)) to serve this function. the oc0a pin is also the output pin for the pwm mode timer function. pcint22: pin change interrupt source 22. the pd6 pin can serve as an external interrupt source. table 4-38. port d pins alternate functions port pin alternate function pd7 ain1 (analog comparator negative input) pcint23 (pin change interrupt 23) pd6 ain0 (analog comparator positive input) oc0a (timer/counter0 output compare match a output) pcint22 (pin change interrupt 22) pd5 t1 (timer/counter 1 ex ternal counter input) oc0b (timer/counter0 output compare match b output) pcint21 (pin change interrupt 21) pd4 xck (usart external clock input/output) t0 (timer/counter 0 ex ternal counter input) pcint20 (pin change interrupt 20) pd3 int1 (external interrupt 1 input) oc2b (timer/counter2 output compare match b output) pcint19 (pin change interrupt 19) pd2 int0 (external interrupt 0 input) pcint18 (pin change interrupt 18) pd1 txd (usart output pin) pcint17 (pin change interrupt 17) pd0 rxd (usart input pin) pcint16 (pin change interrupt 16) 103 4921e?auto?09/09 ata6602/ata6603 ? t1/oc0b/pcint21 ? port d, bit 5 t1, timer/counter1 counter source. oc0b, output compare match output: the pd5 pin can serve as an external output for the timer/counter0 compare match b. the pd5 pin has to be configured as an output (ddd5 set (one)) to serve this function. the oc0b pin is also the output pin for the pwm mode timer function. pcint21: pin change interrupt source 21. the pd5 pin can serve as an external interrupt source. ? xck/t0/pcint20 ? port d, bit 4 xck, usart external clock. t0, timer/counter0 counter source. pcint20: pin change interrupt source 20. the pd4 pin can serve as an external interrupt source. ? int1/oc2b/pcint19 ? port d, bit 3 int1, external interrupt source 1: the pd3 pin can serve as an external interrupt source. oc2b, output compare match output: the pd3 pin can serve as an external output for the timer/counter0 compare match b. the pd3 pin has to be configured as an output (ddd3 set (one)) to serve this function. the oc2b pin is also the output pin for the pwm mode timer function. pcint19: pin change interrupt source 19. the pd3 pin can serve as an external interrupt source. ? int0/pcint18 ? port d, bit 2 int0, external interrupt source 0: the pd2 pin can serve as an external interrupt source. pcint18: pin change interrupt source 18. the pd2 pin can serve as an external interrupt source. ? txd/pcint17 ? port d, bit 1 txd, transmit data (data output pin for the usart). when the usart transmitter is enabled, this pin is configured as an output regardless of the value of ddd1. pcint17: pin change interrupt source 17. the pd1 pin can serve as an external interrupt source. ? rxd/pcint16 ? port d, bit 0 rxd, receive data (data input pin for the usart). when the usart receiver is enabled this pin is configured as an input regardless of the value of ddd0. when the usart forces this pin to be an input, the pull-up can still be controlled by the portd0 bit. pcint16: pin change interrupt source 16. the pd0 pin can serve as an external interrupt source. 104 4921e?auto?09/09 ata6602/ata6603 table 4-39 and table 4-40 relate the alternate functions of port d to the overriding signals shown in figure 4-26 on page 93 . table 4-39. overriding signals for alternate functions pd7..pd4 signal name pd7/ain1 /pcint23 pd6/ain0/ oc0a/pcint22 pd5/t1/oc0b/ pcint21 pd4/xck/ t0/pcint20 puoe0000 puo0000 ddoe 0 0 0 0 ddov 0 0 0 0 pvoe 0 oc0a enable oc0b enable umsel pvov 0 oc0a oc0b xck output dieoe pcint23 ? pcie2 pcint22 ? pc ie2 pcint21 ? pcie2 pcint20 ? pcie2 dieov1111 di pcint23 input pcint22 input pcint21 input t1 input pcint20 input xck input t0 input aio ain1 input ain0 input ? ? table 4-40. overriding signals for alternate functions in pd3..pd0 signal name pd3/oc2b/int1/ pcint19 pd2/int0/ pcint18 pd1/txd/ pcint17 pd0/rxd/ pcint16 puoe 0 0 txen rxen puo 0 0 0 portd0 ? pud ddoe 0 0 txen rxen ddov 0 0 1 0 pvoe oc2b enable 0 txen 0 pvov oc2b 0 txd 0 dieoe int1 enable + pcint19 ? pcie2 int0 enable + pcint18 ? pcie1 pcint17 ? pcie2 pcint16 ? pcie2 dieov1111 di pcint19 input int1 input pcint18 input int0 input pcint17 input pcint16 input rxd aio???? 105 4921e?auto?09/09 ata6602/ata6603 4.10.4 register description for i/o ports 4.10.4.1 the port b data register ? portb 4.10.4.2 the port b data direction register ? ddrb 4.10.4.3 the port b input pins address ? pinb 4.10.4.4 the port c data register ? portc 4.10.4.5 the port c data direction register ? ddrc 4.10.4.6 the port c input pins address ? pinc 4.10.4.7 the port d data register ? portd bit 76543210 portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 portb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 ddrb read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 pinb read/writerrrrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a bit 76543210 ? portc6portc5portc4portc3portc2portc1portc0 portc read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 ddrc read/write r r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ? pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 pinc read/writerrrrrrrr initial value 0 n/a n/a n/a n/a n/a n/a n/a bit 76543210 portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 portd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 106 4921e?auto?09/09 ata6602/ata6603 4.10.4.8 the port d data direction register ? ddrd 4.10.4.9 the port d input pins address ? pind 4.11 external interrupts the external interrupts are triggered by the int0 and int1 pins or any of the pcint23..0 pins. observe that, if enabled, the inte rrupts will trigger even if the in t0 and int1 or pcint23..0 pins are configured as outputs. this feature provides a way of generating a software interrupt. the pin change interrupt pci2 will trigger if an y enabled pcint23..16 pin toggles. the pin change interrupt pci1 will trigger if any enabled pcint14. .8 pin toggles. the pin change interrupt pci0 will trigger if any enabled pcint7..0 pin toggl es. the pcmsk2, pcmsk1 and pcmsk0 regis- ters control which pins contribute to the pin change interrupts. pin change interrupts on pcint23..0 are detected asynchronously. this implies that these interrupts can be used for waking the part also from sleep modes other than idle mode. the int0 and int1 interrupts can be triggered by a falling or rising edge or a low level. this is set up as indicated in the specification for the external interrupt control register a ? eicra. when the int0 or int1 interrupts are enabled and are configured as level triggered, the inter- rupts will trigger as long as the pin is held low. note that recognition of falling or rising edge interrupts on int0 or int1 requires the presence of an i/o clock, described in ?clock systems and their distribution? on page 49 . low level interrupt on int0 and int1 is detected asynchro- nously. this implies that this interrupt can be used for waking the part also from sleep modes other than idle mode. the i/o clock is halted in all sleep modes except idle mode. note that if a level triggered interrupt is used for wake-up from power-down, the required level must be held long enough for the mcu to complete the wake-up to trigger the level interrupt. if the level disappears before the end of the start-up ti me, the mcu will still wake up, but no inter- rupt will be generated. the start- up time is defined by the su t and cksel fuses as described in ?system clock and clock options? on page 49 . bit 76543210 ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 ddrd read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 pind read/write r r rrrrrr initial value n/a n/a n/a n/a n/a n/a n/a n/a 107 4921e?auto?09/09 ata6602/ata6603 4.11.1 external interrupt control register a ? eicra the external interrupt control register a contains control bits for interrupt sense control. ? bit 7..4 ? res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bit 3, 2 ? isc11, isc10: interrupt sense control 1 bit 1 and bit 0 the external interrupt 1 is activated by the exte rnal pin int1 if the sreg i-flag and the cor- responding interrupt mask are set. the level and edges on the external int1 pin that activate the interrupt are defined in table 4-41 . the value on the int1 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an in terrupt. shorter pulses are not guaran teed to generate an interrupt. if low level interrupt is selected, the low level must be held until the completion of the cur- rently executing instruction to generate an interrupt. ? bit 1, 0 ? isc01, isc00: interrupt sense control 0 bit 1 and bit 0 the external interrupt 0 is activated by the exte rnal pin int0 if the sreg i-flag and the cor- responding interrupt mask are set. the level and edges on the external int0 pin that activate the interrupt are defined in table 4-42 . the value on the int0 pin is sampled before detecting edges. if edge or toggle interrupt is selected, pulses that last longer than one clock period will generate an in terrupt. shorter pulses are not guaran teed to generate an interrupt. if low level interrupt is selected, the low level must be held until the completion of the cur- rently executing instruction to generate an interrupt. bit 76543210 ? ? ? ? isc11 isc10 isc01 isc00 eicra read/write r r r r r/w r/w r/w r/w initial value00000000 table 4-41. interrupt 1 sense control isc11 isc10 description 0 0 the low level of int1 generates an interrupt request. 0 1 any logical change on int1 generates an interrupt request. 1 0 the falling edge of int1 generates an interrupt request. 1 1 the rising edge of int1 generates an interrupt request. table 4-42. interrupt 0 sense control isc01 isc00 description 0 0 the low level of int0 generates an interrupt request. 0 1 any logical change on int0 generates an interrupt request. 1 0 the falling edge of int0 generates an interrupt request. 1 1 the rising edge of int0 generates an interrupt request. 108 4921e?auto?09/09 ata6602/ata6603 4.11.2 external interrupt mask register ? eimsk ? bit 7..2 ? res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bit 1 ? int1: external interrupt request 1 enable when the int1 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control1 bits 1/0 (isc11 and isc10) in the external interrupt control register a (e icra) define whether the external interrupt is activated on rising and/or falling edge of the int1 pin or leve l sensed. activity on the pin will cause an interrupt request even if int1 is conf igured as an output. the corresponding inter- rupt of external interrupt request 1 is executed from the int1 interrupt vector. ? bit 0 ? int0: external interrupt request 0 enable when the int0 bit is set (one) and the i-bit in the status register (sreg) is set (one), the external pin interrupt is enabled. the interrupt sense control0 bits 1/0 (isc01 and isc00) in the external interrupt control register a (e icra) define whether the external interrupt is activated on rising and/or falling edge of the int0 pin or leve l sensed. activity on the pin will cause an interrupt request even if int0 is conf igured as an output. the corresponding inter- rupt of external interrupt request 0 is executed from the int0 interrupt vector. 4.11.3 external interrupt flag register ? eifr ? bit 7..2 ? res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bit 1 ? intf1: external interrupt flag 1 when an edge or logic change on the int1 pin triggers an interrupt request, intf1 becomes set (one). if the i-bit in sreg and the int1 bit in eimsk are set (o ne), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is exe- cuted. alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int1 is configured as a level interrupt. ? bit 0 ? intf0: external interrupt flag 0 when an edge or logic change on the int0 pin triggers an interrupt request, intf0 becomes set (one). if the i-bit in sreg and the int0 bit in eimsk are set (o ne), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is exe- cuted. alternatively, the flag can be cleared by writing a logical one to it. this flag is always cleared when int0 is configured as a level interrupt. bit 76543210 ??????int1int0eimsk read/write r r r r r r r/w r/w initial value00000000 bit 76543210 ??????intf1intf0eifr read/write r r r r r r r/w r/w initial value00000000 109 4921e?auto?09/09 ata6602/ata6603 4.11.4 pin change interrupt control register - pcicr ? bit 7..3 - res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bit 2 - pcie2: pin change interrupt enable 2 when the pcie2 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 2 is enabled. any change on any enabled pcint23.. 16 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci2 interrupt vector. pcint23..16 pins are ena bled individually by the pcmsk2 register. ? bit 1 - pcie1: pin change interrupt enable 1 when the pcie1 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 1 is enabled. any change on any enabled pcint14..8 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci1 interrupt vector. pcint14..8 pins are enabled individually by the pcmsk1 register. ? bit 0 - pcie0: pin change interrupt enable 0 when the pcie0 bit is set (one) and the i-bit in the status register (sreg) is set (one), pin change interrupt 0 is enabled. any change on any enabled pcint7..0 pin will cause an interrupt. the corresponding interrupt of pin change interrupt request is executed from the pci0 interrupt vector. pcint7..0 pins are enabled individually by the pcmsk0 register. 4.11.5 pin change interrupt flag register - pcifr ? bit 7..3 - res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bit 2 - pcif2: pin change interrupt flag 2 when a logic change on any pcint23..16 pin triggers an interrupt request, pcif2 becomes set (one). if the i-bit in sreg and the pcie2 bit in pcicr ar e set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is exe- cuted. alternatively, the flag can be cleared by writing a logical one to it. ? bit 1 - pcif1: pin change interrupt flag 1 when a logic change on any pcint14..8 pin tr iggers an interrupt request, pcif1 becomes set (one). if the i-bit in sreg and the pcie1 bit in pcicr ar e set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is exe- cuted. alternatively, the flag can be cleared by writing a logical one to it. bit 76543210 ? ? ? ? ? pcie2 pcie1 pcie0 pcicr read/write r r r r r r/w r/w r/w initial value00000000 bit 76543210 ?????pcif2pcif1pcif0pcifr read/write r r r r r r/w r/w r/w initial value00000000 110 4921e?auto?09/09 ata6602/ata6603 ? bit 0 - pcif0: pin change interrupt flag 0 when a logic change on any pcint7..0 pin triggers an interrupt request, pcif0 becomes set (one). if the i-bit in sreg and the pcie0 bit in pcicr ar e set (one), the mcu will jump to the corresponding interrupt vector. the flag is cleared when the interrupt routine is exe- cuted. alternatively, the flag can be cleared by writing a logical one to it. 4.11.6 pin change mask register 2 ? pcmsk2 ? bit 7..0 ? pcint23..16: pin change enable mask 23..16 each pcint23..16-bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint23..16 is set and the pcie2 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint2 3..16 is cleared, pin change interrupt on the corresponding i/o pin is disabled. 4.11.7 pin change mask register 1 ? pcmsk1 ? bit 7 ? res: reserved bit this bit is an unused bit in the ata660 2/ata6603, and will always read as zero. ? bit 6..0 ? pcint14..8: pin change enable mask 14..8 each pcint14..8-bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint14..8 is set and the pcie 1 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint 14..8 is cleared, pin change interrupt on the corresponding i/o pin is disabled. 4.11.8 pin change mask register 0 ? pcmsk0 ? bit 7..0 ? pcint7..0: pin change enable mask 7..0 each pcint7..0 bit selects whether pin change interrupt is enabled on the corresponding i/o pin. if pcint7..0 is set and the pcie0 bit in pcicr is set, pin change interrupt is enabled on the corresponding i/o pin. if pcint7..0 is cleared, pin change interrupt on the corre- sponding i/o pin is disabled. bit 76543210 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 pcmsk2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ? pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 pcmsk1 read/write r r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 pcmsk0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 111 4921e?auto?09/09 ata6602/ata6603 4.12 8-bit timer/counter0 with pwm timer/counter0 is a general purpose 8-bit time r/counter module, with two independent output compare units, and with pwm support. it allows accurate program execution timing (event man- agement) and wave generation. the main features are: ? two independent output compare units ? double buffered outp ut compare registers ? clear timer on compare match (auto reload) ? glitch free, phase correct pulse width modulator (pwm) ? variable pwm period ? frequency generator ? three independent interrupt sources (tov0, ocf0a, and ocf0b) 4.12.1 overview a simplified block diagram of the 8-bit timer/counter is shown in figure 4-27 . the device-spe- cific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 123 . the prtim0 bit in ?power reduction register - prr? on page 64 must be written to zero to enable timer/counter0 module. figure 4-27. 8-bit timer/counter block diagram timer/counter data bus ocrna ocrnb = = tcntn waveform generation waveform generation ocna ocnb = fixed top value control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb clk tn prescaler t/c oscillator clk i/o tosc1 tosc2 112 4921e?auto?09/09 ata6602/ata6603 4.12.1.1 definitions many register and bit references in this section are written in general form. a lower case ?n? replaces the timer/counter number, in this case 0. a lower case ?x? replaces the output com- pare unit, in this case compare unit a or compare unit b. howe ver, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt0 for accessing timer/counter0 counter value and so on. the definitions in table 4-43 are also used extensively throughout the document. 4.12.1.2 registers the timer/counter (tcnt0) and output compare registers (ocr0a and ocr0b) are 8-bit registers. interrupt request (abbreviated to int.req . in the figure) signals are all visible in the timer interrupt flag register (t ifr0). all interrupts are individually masked with the timer inter- rupt mask register (timsk0). tifr0 and timsk0 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t0 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t0 ). the double buffered output compare registers (ocr0a and ocr0b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform gen- erator to generate a pwm or variable frequency output on the output compare pins (oc0a and oc0b). see ?using the output compare unit? on page 141 for details. the compare match event will also set the compare fl ag (ocf0a or ocf0b) which can be used to gene rate an out- put compare interrupt request. 4.12.2 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs02:0) bits located in the timer/counter control register (tccr0b). for details on clock sources and pres- caler (see ?timer/counter0 and timer/counter1 prescalers? on page 129 ). table 4-43. general counter definitions bottom the counter reaches the bottom when it becomes 0x00. max the counter reaches its maximum when it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr0a register. the assignment is dependent on the mode of operation. 113 4921e?auto?09/09 ata6602/ata6603 4.12.3 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 4-28 shows a block diagram of the counter and its surroundings. figure 4-28. counter unit block diagram signal description (internal signals): count increment or decrement tcnt0 by 1. direction select between increment and decrement. clear clear tcnt0 (set all bits to zero). clk t n timer/counter clock, referred to as clk t0 in the following. top signalize that tcnt0 has reached maximum value. bottom signalize that tcnt0 has reached minimum value (zero). depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t0 ). clk t0 can be generated from an external or internal clock source, selected by the clock select bits (cs02:0). w hen no clock source is selected (cs02:0 = 0) the timer is stopped. however, the tcnt0 value can be accessed by the cpu, regardless of whether clk t0 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm01 and wgm00 bits located in the timer/counter control register (tccr0a) and the wgm02 bit located in the timer/counter control register b (tccr0b). there are clos e connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc0a and oc0b. for more details about advanced counting sequences and waveform generation (see ?modes of operation? on page 116 ). the timer/counter overflow flag (tov0) is set according to the mode of operation selected by the wgm02:0 bits. tov0 can be used for generating a cpu interrupt. data bus tcntn control logic count tovn (int.req.) clock select top tn edge detector (from prescaler) clk tn bottom direction clear 114 4921e?auto?09/09 ata6602/ata6603 4.12.4 output compare unit the 8-bit comparator continuously compares tcnt0 with the output compare registers (ocr0a and ocr0b). whenever tcnt0 equals ocr0a or ocr0b, the comparator signals a match. a match will set the output compare flag (ocf0a or ocf0 b) at the next timer clock cycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is exe- cuted. alternatively, the flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the matc h signal to generate an output according to operating mode set by the wgm02:0 bits and compare output mode (com0x1:0) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see ?modes of operation? on page 116 ). figure 4-29 shows a block diagram of the output compare unit. figure 4-29. output compare unit, block diagram the ocr0x registers are double buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the dou- ble buffering is disabled. the double buffering synchronizes the update of the ocr0x compare registers to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr0x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr0x buffer register, and if double buffering is dis- abled the cpu will access the ocr0x directly. 4.12.4.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force outp ut compare (foc0x) bit. forci ng compare match will not set the ocf0x flag or reload/clear the timer, but the oc0x pin will be updated as if a real compare match had occurred (the com0x1:0 bits settings de fine whether the oc0x pin is set, cleared or toggled). ocfnx (int.req.) = (8-bit comparator) ocrnx ocnx data bus tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 115 4921e?auto?09/09 ata6602/ata6603 4.12.4.2 compare match blocking by tcnt0 write all cpu write operations to th e tcnt0 register will block any co mpare match that occur in the next timer clock cycle, even when the timer is stopped. this feature allows ocr0x to be initial- ized to the same value as tcnt0 without triggering an interrupt when the timer/counter clock is enabled. 4.12.4.3 using the output compare unit since writing tcnt0 in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changing tc nt0 when using the output compare unit, independently of whether the timer/counter is running or not. if the value written to tcnt0 equals the ocr0x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt0 value equal to bottom when the counter is downcounting. the setup of the oc0x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc0x value is to use the force output com- pare (foc0x) strobe bits in normal mode. the oc0x registers keep their values even when changing between waveform generation modes. be aware that the com0x1:0 bits are not doubl e buffered together with the compare value. changing the com0x1:0 bits will take effect immediately. 4.12.5 compare match output unit the compare output mode (com0x1:0) bits have two functions. the waveform generator uses the com0x1:0 bits for defining the output compare (oc0x) state at the next compare match. also, the com0x1:0 bits control the oc0x pin output source. figure 4-30 shows a simplified schematic of the logic affected by the com0x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com0x1:0 bits are shown. when referring to the oc0x state, the reference is for the internal oc0x register, not the oc0x pin. if a system reset occur, the oc0x register is reset to ?0?. figure 4-30. compare match output unit, schematic port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data bus focnx clk i/o 116 4921e?auto?09/09 ata6602/ata6603 the general i/o port function is overridden by the output compare (oc0x) from the waveform generator if either of the com0x1:0 bits are set. however, the oc0x pin direction (input or out- put) is still controlled by the da ta direction register (ddr) for th e port pin. the data direction register bit for the oc0x pin (ddr_oc0x) must be set as output before the oc0x value is visi- ble on the pin. the port override function is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc0x state before the out- put is enabled. note that some com0x1:0 bi t settings are reserved for certain modes of operation (see ?8-bit timer/counter register description? on page 123 ). 4.12.5.1 compare output mode and waveform generation the waveform generator uses the com0x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com0x1:0 = 0 tells the waveform generator that no action on the oc0x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 4-44 on page 123 . for fast pwm mode, refer to table 4-45 on page 123 , and for phase correct pwm refer to table 4-46 on page 124 . a change of the com0x1:0 bits st ate will have effect at the first compare matc h after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc0x strobe bits. 4.12.6 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm02:0) and compare output mode (com0x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com0x1:0 bits control whether the pwm out- put generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com0x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (see ?compare match output unit? on page 115 ). for detailed timing information refer to ?timer/counter timing diagrams? on page 121 . 4.12.6.1 normal mode the simplest mode of operation is the normal mode (wgm02:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bot- tom (0x00). in normal o peration the timer/counter overflow flag (tov0) will be set in the same timer clock cycle as the tcnt0 becomes zero. the tov0 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov0 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 117 4921e?auto?09/09 ata6602/ata6603 4.12.6.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm 02:0 = 2), the ocr0a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt0) matches the ocr0a. the ocr0a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 4-31 . the counter value (tcnt0) increases until a compare match occurs between tcnt0 and ocr0a, and then counter (tcnt0) is cleared. figure 4-31. ctc mode, timing diagram an interrupt can be generated each time the counter value reaches the top value by using the ocf0a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a va lue close to bottom when the counter is run- ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr0a is lower than the current value of tcnt0, the counter will miss the compar e match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc0a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com0a1:0 = 1). the oc0a value will not be visible on the port pin unless the data direction for the pin is set to output. the waveform ge nerated will have a ma ximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov0 flag is set in the same timer clock cycle that the counter counts from max to 0x00. tcntn ocn (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------------- = 118 4921e?auto?09/09 ata6602/ata6603 4.12.6.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm02:0 = 3 or 7) provides a high fre- quency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to top then restarts from bot- tom. top is defined as 0xff when wgm2:0 = 3, and ocr0a when wgm2:0 = 7. in non-inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that use dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac app lications. high frequency a llows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 4-32 . the tcnt0 value is in the timing diagram shown as a his- togram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. figure 4-32. fast pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches top. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com0x1:0 to three: setting the com0a1:0 bits to one allows the oc0a pin to toggle on compare matches if th e wgm02 bit is set. this option is not available for the oc0b pin (see table 4-48 on page 124 ). the actual oc0x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is gener- ated by setting (or clearing) the oc0x register at the compare match between ocr0x and tcnt0, and clearing (or setting) the oc0x regist er at the timer clock cycle the counter is cleared (changes from top to bottom). tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocn ocn (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 119 4921e?auto?09/09 ata6602/ata6603 the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr0a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr0a equal to max will result in a constantly high or low output (depending on the polarity of the output set by the com0a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by set- ting oc0x to toggle its logical level on each compare match (com0x1:0 = 1). the waveform generated will have a maximum frequency of f oc0 = f clk_i/o /2 when ocr0a is set to zero. this feature is similar to the oc0a toggle in ctc mode, except the double buffer feature of the out- put compare unit is enabled in the fast pwm mode. 4.12.6.4 phase correct pwm mode the phase correct pwm mode (wgm02:0 = 1 or 5) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bot- tom. top is defined as 0xff when wgm2:0 = 1, and ocr0a when wgm2:0 = 5. in non-inverting compare output mode, the output compare (oc0x) is cleared on the compare match between tcnt0 and ocr0x while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor con- trol applications. in phase correct pwm mode the counter is incremented until the counter value matches top. when the counter reaches top, it changes the count direction. the tcnt0 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 4-33 on page 120 . the tcnt0 value is in the timing diagram shown as a histogram for illustrating the dual-sl ope operation. the diagram includes non-invert ed and inverted pwm out- puts. the small horizontal line marks on the tcnt0 slopes represent compare matches between ocr0x and tcnt0. f ocnxpwm f clk_i/o n 256 ? -------------------- - = 120 4921e?auto?09/09 ata6602/ata6603 figure 4-33. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov0) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc0x pins. setting the com0x1:0 bits to two will produce a non-inverted pwm. an inverted pwm output can be generated by setting the com0x1:0 to three: setting the com0a0 bits to one allows the oc0a pin to toggle on compare ma tches if the wgm02 bit is set. this option is not available for the oc0b pin (see table 4-49 on page 125 ). the actual oc0x value will only be visible on the port pin if the data direction for th e port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc0x register at the compare match between ocr0x and tcnt0 when the counter increments, and setting (or clearing) the oc0x register at compare match between ocr0x and tcnt0 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 64, 256, or 1024). the extreme values for the ocr0a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr0a is set equal to bottom, the output will be continuously low an d if set equal to max the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocn ocn (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update f ocnxpcpwm f clk_i/o n 510 ? -------------------- - = 121 4921e?auto?09/09 ata6602/ata6603 at the very start of period 2 in figure 4-33 on page 120 ocnx has a transition from high to low even though there is no compare match. the poin t of this transition is to guarantee symmetry around bottom. there are two cases that give a transition without compare match. ? ocrnx changes its value from max, like in figure 4-33 on page 120 . when the ocr0a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocnx value at max must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocrnx, and for that reason misses the compare match and hence the ocnx change that would have happened on the way up. 4.12.7 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t0 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set. figure 4-34 contains timing data for basic timer/counter operation. the figure shows the count sequence close to the max val ue in all modes other than phase correct pwm mode. figure 4-34. timer/counter timing diagram, no prescaling figure 4-35 shows the same timing data, but with the prescaler enabled. figure 4-35. timer/counter timing dia gram, with prescaler (f clk_i/o /8) clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) 122 4921e?auto?09/09 ata6602/ata6603 figure 4-36 shows the setting of ocf0b in all m odes and ocf0a in all modes except ctc mode and pwm mode, where ocr0a is top. figure 4-36. timer/counter timing diagram, setting of ocf0x, with prescaler (f clk_i/o /8) figure 4-37 shows the setting of ocf0a and the clearing of tcnt0 in ctc mode and fast pwm mode where ocr0a is top. figure 4-37. timer/counter timing diagram, clear timer on compare match mode, with pres- caler (f clk_i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clktn (clk i/o /8) 123 4921e?auto?09/09 ata6602/ata6603 4.12.8 8-bit timer/counte r register description 4.12.8.1 timer/coun ter control regi ster a ? tccr0a ? bits 7:6 ? com0a1:0: compare match output a mode these bits control the output compare pin (oc0a) behavior. if one or both of the com0a1:0 bits are set, the oc0a output over rides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit correspond- ing to the oc0a pin must be set in order to enable the output driver. when oc0a is connected to the pin, the function of the com0a1:0 bits depends on the wgm02:0 bit setting. table 4-44 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 4-45 shows the com0a1:0 bit functionality when the wgm01:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 118 for more details. bit 7 6 5 4 3 210 com0a1 com0a0 com0b1 com0b0 ? ? wgm01 wgm00 tccr0a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 4-44. compare output mode, non-pwm mode com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc0a on compare match 1 0 clear oc0a on compare match 1 1 set oc0a on compare match table 4-45. compare output mode, fast pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port oper ation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 1 0 clear oc0a on compare match, set oc0a at top 1 1 set oc0a on compare match, clear oc0a at top 124 4921e?auto?09/09 ata6602/ata6603 table 4-46 shows the com0a1:0 bit functionality when the wgm02:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs when ocr0a equals top and com0a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 147 for more details. ? bits 5:4 ? com0b1:0: compare match output b mode these bits control the output compare pin (oc0b) behavior. if one or both of the com0b1:0 bits are set, the oc0b output over rides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit correspond- ing to the oc0b pin must be set in order to enable the output driver. when oc0b is connected to the pin, the function of the com0b1:0 bits depends on the wgm02:0 bit setting. table 4-47 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to a normal or ctc mode (non-pwm). table 4-48 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 118 for more details. table 4-46. compare output mode, phase correct pwm mode (1) com0a1 com0a0 description 0 0 normal port operation, oc0a disconnected. 01 wgm02 = 0: normal port operation, oc0a disconnected. wgm02 = 1: toggle oc0a on compare match. 10 clear oc0a on compare match when up-counting. set oc0a on compare match when down-counting. 11 set oc0a on compare match when up-counting. clear oc0a on compare match when down-counting. table 4-47. compare output mode, non-pwm mode com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 0 1 toggle oc0b on compare match 1 0 clear oc0b on compare match 1 1 set oc0b on compare match table 4-48. compare output mode, fast pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 1 0 clear oc0b on compare match, set oc0b at top 1 1 set oc0b on compare match, clear oc0b at top 125 4921e?auto?09/09 ata6602/ata6603 table 4-49 shows the com0b1:0 bit functionality when the wgm02:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs when ocr0b equals top and com0b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 119 for more details. ? bits 3, 2 ? res: reserved bits these bits are reserved bits in the ata 6602/ata6603 and will always read as zero. ? bits 1:0 ? wgm01:0: waveform generation mode combined with the wgm02 bit found in the tc cr0b register, these bits control the count- ing sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used (see table 4-50 ). modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see ?modes of operation? on page 116 ). notes: 1. max = 0xff 2. bottom = 0x00 table 4-49. compare output mode, phase correct pwm mode (1) com0b1 com0b0 description 0 0 normal port operation, oc0b disconnected. 01reserved 10 clear oc0b on compare match when up-counting. set oc0b on compare match when down-counting. 11 set oc0b on compare match when up-counting. clear oc0b on compare match when down-counting. table 4-50. waveform generation mode bit description mode wgm02 wgm01 wgm00 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 10 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff top max 4 1 0 0 reserved ? ? ? 51 0 1 pwm, phase correct ocra top bottom 6 1 1 0 reserved ? ? ? 7 1 1 1 fast pwm ocra top top 126 4921e?auto?09/09 ata6602/ata6603 4.12.8.2 timer/coun ter control regi ster b ? tccr0b ? bit 7 ? foc0a: force output compare a the foc0a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode . when writing a logi cal one to the foc0a bit, an immediate compare match is forced on the waveform generation unit. the oc0a output is changed according to its com0a1:0 bits setting. note that the foc0a bit is imple- mented as a strobe. therefore it is the value present in the com0a1:0 bits that determines the effect of the forced compare. a foc0a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0a as top. the foc0a bit is always read as zero. ? bit 6 ? foc0b: force output compare b the foc0b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr0b is written when operating in pwm mode . when writing a logi cal one to the foc0b bit, an immediate compare match is forced on the waveform generation unit. the oc0b output is changed according to its com0b1:0 bits setting. note that the foc0b bit is imple- mented as a strobe. therefore it is the value present in the com0b1:0 bits that determines the effect of the forced compare. a foc0b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr0b as top. the foc0b bit is always read as zero. ? bits 5:4 ? res: reserved bits these bits are reserved bits in the ata 6602/ata6603 and will always read as zero. ? bit 3 ? wgm02: waveform generation mode see the description in the ?timer/counter control register a ? tccr0a? on page 123 . ? bits 2:0 ? cs02:0: clock select the three clock select bits select the clock source to be used by the timer/counter. bit 7 6 5 4 3 210 foc0a foc0b ? ? wgm02 cs02 cs01 cs00 tccr0b read/write w w r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 127 4921e?auto?09/09 ata6602/ata6603 if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 4.12.8.3 timer/counter register ? tcnt0 the timer/counter register gives direct ac cess, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt0 register blocks (removes) the compare match on the following timer clock. modifying the counter (tcnt0) while the counter is running, introduces a risk of missing a compare match between tcnt0 and the ocr0x registers. 4.12.8.4 output compare register a ? ocr0a the output compare register a contains an 8-bi t value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0a pin. 4.12.8.5 output compare register b ? ocr0b the output compare register b contains an 8-bi t value that is continuously compared with the counter value (tcnt0). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc0b pin. table 4-51. clock select bit description cs02 cs01 cs00 description 0 0 0 no clock source (timer/counter stopped) 001clk i/o /(no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t0 pin. clock on falling edge. 1 1 1 external clock source on t0 pin. clock on rising edge. bit 76543210 tcnt0[7:0] tcnt0 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr0a[7:0] ocr0a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr0b[7:0] ocr0b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 128 4921e?auto?09/09 ata6602/ata6603 4.12.8.6 timer/counter interrupt mask register ? timsk0 ? bits 7..3 ? res: reserved bits these bits are reserved bits in the ata 6602/ata6603 and will always read as zero. ? bit 2 ? ocie0b: timer/counter output compare match b interrupt enable when the ocie0b bit is written to one, and the i-bit in the status register is set, the timer/counter compare match b interrupt is enabled. the corresponding interrupt is exe- cuted if a compare match in timer/counter occurs, i.e., when the ocf0b bit is set in the timer/counter interrupt flag register ? tifr0. ? bit 1 ? ocie0a: timer/counter0 output compare match a interrupt enable when the ocie0a bit is written to one, and the i-bit in the status register is set, the timer/counter0 compare match a interrupt is enabled. the corresponding interrupt is exe- cuted if a compare match in timer/counter0 occurs, i.e., when the ocf0a bit is set in the timer/counter 0 interrupt flag register ? tifr0. ? bit 0 ? toie0: timer/counter0 overflow interrupt enable when the toie0 bit is written to one, and the i-bit in the status register is set, the timer/counter0 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter0 occurs, i.e., when the tov0 bit is set in the timer/counter 0 interrupt flag register ? tifr0. 4.12.8.7 timer/counter 0 interrupt flag register ? tifr 0 ? bits 7..3 ? res: reserved bits these bits are reserved bits in the ata 6602/ata6603 and will always read as zero. ? bit 2 ? ocf0b: timer/counter 0 output compare b match flag the ocf0b bit is set when a compare match occurs between the timer/counter and the data in ocr0b ? output compare register0 b. ocf0b is cleared by hardware when exe- cuting the corresponding interrupt handling vector. alternatively, ocf0b is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0b (timer/counter compare b match interrupt enable), and ocf0b are set, the timer/counter compare match interrupt is executed. ? bit 1 ? ocf0a: timer/counter 0 output compare a match flag the ocf0a bit is set when a compare match occurs between the timer/counter0 and the data in ocr0a ? output compare register0. ocf0a is cleared by hardware when execut- ing the corresponding interrupt handling vector. alternatively, ocf0a is cleared by writing a logic one to the flag. when the i-bit in sreg, ocie0a (timer/counter0 compare match interrupt enable), and ocf0a are set, the timer/counter0 compare match interrupt is executed. bit 76543 210 ? ? ? ? ? ocie0b ocie0a toie0 timsk0 read/write r r r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ?????ocf0bocf0atov0tifr0 read/write r r r r r r/w r/w r/w initial value00000000 129 4921e?auto?09/09 ata6602/ata6603 ? bit 0 ? tov0: timer/counter0 overflow flag the bit tov0 is set when an overflow occurs in timer/counter0. tov0 is cleared by hard- ware when executing the corresponding interrupt handling vector. alternatively, tov0 is cleared by writing a logic one to the flag. when the sreg i-bit, toie0 (timer/counter0 overflow interrupt enable), and tov0 are set, the timer/counter0 overflow interrupt is executed. the setting of this flag is dependent of the wgm02:0 bit setting. refer to table 4-50 on page 125 and ?waveform generation mode bit description? on page 125 . 4.13 timer/counter0 and timer/counter1 prescalers timer/counter1 and timer/counter0 share the same prescaler module, but the timer/counters can have different prescaler settings. the description below applies to both timer/counter1 and timer/counter0. 4.13.1 internal clock source the timer/counter can be clocked directly by the system clock (by setting the csn2:0 = 1). this provides the fastest operation, with a maximum timer/counter clock frequency equal to system clock frequency (f clk_i/o ). alternatively, one of four taps from the prescaler can be used as a clock source. the prescaled clock has a frequency of either f clk_i/o /8, f clk_i/o /64, f clk_i/o /256, or f clk_i/o /1024. 4.13.2 prescaler reset the prescaler is free running, i.e., operates independently of the clock select logic of the timer/counter, and it is shared by timer/counter1 and timer/counter0. since the prescaler is not affected by the timer/counter? s clock select, the state of t he prescaler will have implications for situations where a prescaled clock is used. one example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler (6 > csn2:0 > 1). the number of system clock cycles from when the timer is enabled to the first count occurs can be from 1 to n+1 system clock cycles, where n equals the prescaler divisor (8, 64, 256, or 1024). it is possible to use the prescaler reset for synchronizing the timer/counter to program execu- tion. however, care must be taken if the other timer/counter that shares the same prescaler also uses prescaling. a prescaler reset will affect the prescaler period for all timer/coun ters it is connected to. 4.13.3 external clock source an external clock source applied to the t1/t0 pin can be used as timer/counter clock (clk t1 /clk t0 ). the t1/t0 pin is sampled once every system clock cycle by the pin synchronization logic. the synchronized (sampled) signal is then passed through the edge detector. figure 4-38 on page 130 shows a functional equivalent block diagram of the t1/t0 synchronization and edge detector logic. the registers are clocked at the positive edge of the internal system clock ( clk i/o ). the latch is transparent in the high period of the internal system clock. the edge detector generates one clk t1 /clk t 0 pulse for each positive (csn2:0 = 7) or negative (csn2:0 = 6) edge it detects. 130 4921e?auto?09/09 ata6602/ata6603 figure 4-38. t1/t0 pin sampling the synchronization and e dge detector logic introduces a de lay of 2.5 to 3.5 system clock cycles from an edge has been applied to the t1/t0 pin to the counter is updated. enabling and disabling of the clock input must be done when t1/t0 has been stable for at least one system clock cycle, otherwise it is a risk t hat a false timer/counter clock pulse is generated. each half period of the external clock applie d must be longer than one system clock cycle to ensure correct sampling. the external clock must be guaranteed to have less than half the sys- tem clock frequency (f extclk < f clk_i/o /2) given a 50/50% duty cycle. since the edge detector uses sampling, the maximum frequency of an external clock it can detect is half the sampling fre- quency (nyquist sampling theorem). however, due to variation of the system clock frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) tolerances, it is recommended that maximum frequency of an external clock source is less than f clk_i/o /2.5. an external clock source can not be prescaled. figure 4-39. prescaler for timer/counter0 and timer/counter1 (1) note: 1. the synchronization logic on the input pins ( t1/t0) is shown in figure 4-38 . tn_sync (to clock select logic) edge detector synchronization dq dq le dq tn clk i/o psrsync clear t1 t0 clk i/o synchronization synchronization cs10 cs11 cs12 0 timer/counter1 clock source clk t1 timer/counter0 clock source clk t0 cs00 cs01 cs02 0 ck/8 ck/64 ck/256 ck/1024 10-bit t/c prescaler 131 4921e?auto?09/09 ata6602/ata6603 4.13.4 general timer/counter control register ? gtccr ? bit 7 ? tsm: timer/counter synchronization mode writing the tsm bit to one activates the timer/ counter synchronization mode. in this mode, the value that is wr itten to the psrasy and psrsync bits is kept, hence keeping the cor- responding prescaler reset signals asserted. this ensures that the corresponding timer/counters are halted and can be configured to the same value without the risk of one of them advancing during configuration. w hen the tsm bit is written to zero, the psrasy and psrsync bits are cleared by hardware, and the timer/counters start counting simultaneously. ? bit 0 ? psrsync: prescaler reset when this bit is one, timer/ counter1 and timer/counter0 pre scaler will be reset. this bit is normally cleared immediately by hardware, except if the tsm bit is set. note that timer/counter1 and timer/counter0 share the same prescaler and a reset of this prescaler will affect both timers. 4.14 16-bit timer/counter1 with pwm the 16-bit timer/counter unit allows accurate program execution timing (event management), wave generation, and signal timing measurement. the main features are: ? true 16-bit design (i.e., allows 16-bit pwm) ? two independent output compare units ? double buffered outp ut compare registers ? one input capture unit ? input capture noise canceler ? clear timer on compare match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? variable pwm period ? frequency generator ? external event counter ? four independent interrupt sources (tov1, ocf1a, ocf1b, and icf1) 4.14.1 overview most register and bit references in this sect ion are written in general form. a lower case ?n? replaces the timer/counter number, and a lower case ?x? replaces the output compare unit channel. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt1 for accessing timer/counter1 counter value and so on. a simplified block diagram of the 16-bit timer/counter is shown in figure 4-40 on page 132 . the device-specific i/o register and bit locations are listed in the ?16-bit timer/counter register description? on page 153 . the prtim1 bit in ?power reduction register - prr? on page 64 must be written to zero to enable timer/counter1 module. bit 765432 1 0 tsm ? ? ? ? ? psrasy psrsync gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 132 4921e?auto?09/09 ata6602/ata6603 figure 4-40. 16-bit timer/counter block diagram (1) note: 1. refer to table 4-32 on page 95 and table 4-38 on page 102 for timer/counter1 pin placement and description. 4.14.1.1 registers the timer/counter (tcnt1), output compare registers (ocr1a/b), and input capture regis- ter (icr1) are all 16-bit registers. special pr ocedures must be followed when accessing the 16-bit registers. these procedures are described in the section ?accessing 16-bit registers? on page 133 . the timer/counter co ntrol registers (tccr1a/b) are 8-bit registers and have no cpu access restrictions. interrupt requests (abbrevi ated to int.req. in the figure) signals are all visible in the timer interrupt flag register (tifr1). all interrupts are individually masked with the timer interrupt mask register (timsk1). tifr1 and timsk1 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or by an external clock source on the t1 pin. the clock select logic block controls which clock source and edge the timer/counter uses to increment (or decrement) its value. the timer/counter is inactive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t 1 ). clock select timer/counter data b u s ocrna ocrnb icrn = = tcntn waveform generation waveform generation ocna ocnb noise canceler icpn = fixed top values edge detector control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) icfn (int.req.) tccrna tccrnb (from analog comparator ouput) tn edge detector (from prescaler) clk tn 133 4921e?auto?09/09 ata6602/ata6603 the double buffered output compare registers (ocr1a/b) are compared with the timer/coun- ter value at all time. the result of the compare can be used by the waveform generator to generate a pwm or variable frequency output on the output compare pin (oc1a/b), see ?out- put compare units? on page 140 . the compare match event will also set the compare match flag (ocf1a/b) which can be used to generate an output compare interrupt request. the input capture register can capture the timer/ counter value at a given external (edge trig- gered) event on either the input capture pin (icp1) or on the analog comparator pins (see ?analog comparator? on page 260 ). the input capture unit includes a digital filtering unit (noise canceler) for reducing the chance of capturing noise spikes. the top value, or maximum timer/counter value, can in some modes of operation be defined by either the ocr1a register, the icr1 regist er, or by a set of fixed values. when using ocr1a as top value in a pwm mode, the ocr1a register can not be used for generating a pwm output. however, the top value will in this case be do uble buffered allowing the top value to be changed in run time. if a fixed top value is required, the icr1 register can be used as an alternative, freeing the ocr1a to be used as pwm output. 4.14.1.2 definitions the following definitions are used extensively throughout the section: table 4-52. general counter definitions 4.14.2 accessing 16-bit registers the tcnt1, ocr1a/b, and icr1 are 16-bit registers that can be accessed by the avr cpu via the 8-bit data bus. the 16-bit register must be byte accessed using two read or write operations. each 16-bit timer has a single 8-bit register for temporary storing of the high byte of the 16-bit access. the same temporary register is shared between all 16-bit registers within each 16-bit timer. accessing the low byte triggers the 16-bit read or write operation. when the low byte of a 16-bit register is written by the cpu, the high byte stored in the temporary register, and the low byte written are both copied into the 16-bit register in the same clock cycle. when the low byte of a 16-bit register is read by the cpu, the high by te of the 16-bit register is copied into the tempo- rary register in the same clock cycle as the low byte is read. not all 16-bit accesses uses the temporary register for the high byte. reading the ocr1a/b 16-bit registers does not involve using the temporary register. to do a 16-bit write, the high byte must be written before the low byte. for a 16-bit read, the low byte must be read before the high byte. the following code examples show how to access the 16-bit timer registers assuming that no interrupts updates the temporary register. the same principle can be used directly for accessing the ocr1a/b and icr1 registers. note that when using ?c?, the compiler handles the 16-bit access. bottom the counter reaches the bottom when it becomes 0x0000. max the counter reaches its max imum when it becomes 0xffff (decimal 65535). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be one of the fixed values: 0x00ff, 0x01ff, or 0x03ff, or to the value stored in the o cr1a or icr1 register. the assignment is depen- dent of the mode of operation. 134 4921e?auto?09/09 ata6602/ata6603 note: 1. the example code assumes that the pa rt specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ? sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt1 value in the r17:r16 register pair. it is important to notice that accessing 16-bit registers are atomic operations. if an interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of the 16-bit timer regis- ters, then the result of the a ccess outside the interrupt will be corrupted. theref ore, when both the main code and the interrupt code update the temporary register, the main code must disable the interrupts during the 16-bit access. the following code examples show how to do an atomic read of the tcnt1 register contents. reading any of the ocr1a/b or icr1 registers can be done by using the same principle. assembly code examples (1) ... ; set tcnt 1 to 0x01ff ldi r17,0x01 ldi r16,0xff out tcnt 1 h,r17 out tcnt 1 l,r16 ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ... c code examples (1) unsigned int i; ... /* set tcnt 1 to 0x01ff */ tcnt 1 = 0x1ff; /* read tcnt 1 into i */ i = tcnt 1 ; ... 135 4921e?auto?09/09 ata6602/ata6603 note: 1. the example code assumes that the pa rt specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ? sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example returns the tcnt1 value in the r17:r16 register pair. assembly code example (1) tim16_readtcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; read tcnt 1 into r17:r16 in r16,tcnt 1 l in r17,tcnt 1 h ; restore global interrupt flag out sreg,r18 ret c code example (1) unsigned int tim16_readtcnt 1 ( void ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* read tcnt 1 into i */ i = tcnt 1 ; /* restore global interrupt flag */ sreg = sreg; return i; } 136 4921e?auto?09/09 ata6602/ata6603 the following code examples show how to do an atomic write of the tcnt1 register contents. writing any of the ocr1a/b or icr1 register s can be done by using the same principle. note: 1. the example code assumes that the pa rt specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ? sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the assembly code example requires that the r17:r16 register pair contains the value to be writ- ten to tcnt1. 4.14.2.1 reusing the temporary high byte register if writing to more than one 16-bit register where the high byte is the same for all registers written, then the high byte only needs to be written once. however, note that the same rule of atomic operation described previously also applies in this case. assembly code example (1) tim16_writetcnt 1 : ; save global interrupt flag in r18,sreg ; disable interrupts cli ; set tcnt 1 to r17:r16 out tcnt 1 h,r17 out tcnt 1 l,r16 ; restore global interrupt flag out sreg,r18 ret c code example (1) void tim16_writetcnt 1 ( unsigned int i ) { unsigned char sreg; unsigned int i; /* save global interrupt flag */ sreg = sreg; /* disable interrupts */ _cli(); /* set tcnt 1 to i */ tcnt 1 = i; /* restore global interrupt flag */ sreg = sreg; } 137 4921e?auto?09/09 ata6602/ata6603 4.14.3 timer/counter clock sources the timer/counter can be clocked by an internal or an external clock source. the clock source is selected by the clock select logic which is controlled by the clock select (cs12:0) bits located in the timer/counter control register b (tccr1b). for details on clock sources and prescaler (see ?timer/counter0 and timer/counter1 prescalers? on page 129 ). 4.14.4 counter unit the main part of the 16-bit timer/counter is th e programmable 16-bit bi-directional counter unit. figure 4-41 shows a block diagram of the counter and its surroundings. figure 4-41. counter unit block diagram signal description (internal signals): count increment or decrement tcnt1 by 1. direction select between increment and decrement. clear clear tcnt1 (set all bits to zero). clk t 1 timer/counter clock. top signalize that tcnt1 has reached maximum value. bottom signalize that tcnt1 has reached minimum value (zero). the 16-bit counter is mapped into two 8-bit i/o memory locations: counter high (tcnt1h) con- taining the upper eight bits of the counter, and counter low (tcnt1l) containing the lower eight bits. the tcnt1h register can only be indirect ly accessed by the cpu. when the cpu does an access to the tcnt1h i/o location, the cpu accesses the high byte temporary register (temp). the temporary register is updated with the tcnt1h value when the tcnt1l is read, and tcnt1h is updated with the temporary register va lue when tcnt1l is written. this allows the cpu to read or write the entire 16-bit counter value within one clock cycle via the 8-bit data bus. it is important to notice that there are special cases of writing to the tcnt1 register when the counter is counting that will gi ve unpredictable results. the s pecial cases are described in the sections where they are of importance. depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t 1 ). the clk t 1 can be generated from an external or internal clock source, selected by the clock select bits (cs12:0). when no clock source is selected (cs12:0 = 0) the timer is stopped. however, the tcnt1 value can be accessed by the cpu, independent of whether clk t 1 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. temp (8-bit) data bus (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) control logic count clear direction tovn (int.req.) clock select top bottom tn edge detector (from prescaler) clk tn 138 4921e?auto?09/09 ata6602/ata6603 the counting sequence is determined by the setting of the waveform generation mode bits (wgm13:0) located in the timer/counter control registers a and b (tccr1a and tccr1b). there are close connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc1x. for more details about advanced counting sequences and waveform generation (see ?modes of operation? on page 143 ). the timer/counter overflow flag (tov1) is set according to the mode of operation selected by the wgm13:0 bits. tov1 can be used for generating a cpu interrupt. 4.14.5 input capture unit the timer/counter incorporates an input capture unit that can capture external events and give them a time-stamp indicating time of occurrence. the external signal indicating an event, or mul- tiple events, can be applied via the icp1 pin or al ternatively, via the analog-comparator unit. the time-stamps can then be used to calculate frequenc y, duty-cycle, and other features of the sig- nal applied. alternatively the time-stamps can be used for creating a log of the events. the input capture unit is illustrated by the block diagram shown in figure 4-42 . the elements of the block diagram that are not directly a part of the input capture unit are gray shaded. the small ?n? in register and bit names indicates the timer/counter number. figure 4-42. input capture unit block diagram when a change of the logic level (an event) occurs on the input capture pin (icp1), alternatively on the analog comparator output (aco), and this change confirms to the setting of the edge detector, a capture will be triggered. when a captur e is triggered, the 16-bit value of the counter (tcnt1) is written to the input capture register (icr1). the input capture flag (icf1) is set at the same system clock as the tcnt1 value is copi ed into icr1 register. if enabled (icie1 = 1), the input capture flag generates an input capture interrupt. the icf1 flag is automatically cleared when the interrupt is executed. alternatively the icf1 flag can be cleared by software by writing a logical one to its i/o bit location. icfn (int.req.) analog comparator write icrn (16-bit register) icrnh (8-bit) noise canceler icpn edge detector temp (8-bit) data bus (8-bit) icrnl (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) acic* icnc ices aco* 139 4921e?auto?09/09 ata6602/ata6603 reading the 16-bit value in the input capture register (icr1) is done by first reading the low byte (icr1l) and then the high byte (icr1h). when the low byte is read the high byte is copied into the high byte temporary regi ster (temp). when the cpu reads the icr1h i/o location it will access the temp register. the icr1 register can only be written when us ing a waveform generation mode that utilizes the icr1 register for defining the counter?s top value. in these cases the waveform genera- tion mode (wgm13:0) bits must be set before the top value can be written to the icr1 register. when writing the icr1 re gister the high byte must be written to the icr1h i/o location before the low byte is written to icr1l. for more information on how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 133 . 4.14.5.1 input capture trigger source the main trigger source for the input capture unit is the input capture pin (icp1). timer/counter1 can alternatively use the analog comparator output as trigger source for the input capture unit. the analog comparator is selected as trigger source by setting the analog comparator input capture (acic) bit in the analog comparator control and status register (acsr). be aware that changing trigger source can trigger a capture. the input capture flag must therefore be cleared after the change. both the input capture pin (icp1) and the analog comparator output (aco) inputs are sampled using the same technique as for the t1 pin (see figure 4-38 on page 130 ). the edge detector is also identical. however, when the noise canceler is enabled, additional logic is inserted before the edge detector, which increase s the delay by four system clock cycles. note that the input of the noise canceler and edge detector is always enabled unless the timer/counter is set in a waveform generation mode that uses icr1 to define top. an input capture can be trigger ed by software by controlling the port of the icp1 pin. 4.14.5.2 noise canceler the noise canceler improves noise immunity by using a simple digital filtering scheme. the noise canceler input is monitored over four samples, and all four must be equal for changing the output that in turn is used by the edge detector. the noise canceler is enabled by setting the input capture noise canceler (icnc1) bit in timer/counter control register b (tccr1b). when enabled the noise canceler introduces addi- tional four system clock cycles of delay from a change applied to the input, to the update of the icr1 register. the noise canceler uses the sy stem clock and is therefore not affected by the prescaler. 4.14.5.3 using the input capture unit the main challenge when using the input capture unit is to assign enough processor capacity for handling the incoming events. the time between two events is critical. if the processor has not read the captured value in th e icr1 register before the nex t event occurs, the icr1 will be overwritten with a new value. in this case the result of the ca pture will be incorrect. when using the input capture interrupt, the icr1 register should be read as early in the inter- rupt handler routine as possible. even though the input capture interrupt has relatively high priority, the maximum interrupt response time is dependent on the maximum number of clock cycles it takes to handle any of the other interrupt requests. 140 4921e?auto?09/09 ata6602/ata6603 using the input capture unit in any mode of operation when the top value (resolution) is actively changed during operation, is not recommended. measurement of an external signal?s duty cycle requires that the trigger edge is changed after each capture. changing the edge sensing must be done as early as possible after the icr1 register has been read. after a change of the edge, the input capture flag (icf1) must be cleared by software (writing a logical one to the i/o bit location). for measuring frequency only, the clearing of the icf1 flag is not required (if an interrupt handler is used). 4.14.6 output compare units the 16-bit comparator continuously compares tcnt1 with the output compare register (ocr1x). if tcnt equals ocr1x the comparator signals a match. a match will set the output compare flag (ocf1x) at the next timer clock cycle. if enabled (ocie1x = 1), the output com- pare flag generates an output compare interrupt. the ocf1x flag is automatically cleared when the interrupt is executed. alternatively the ocf1x flag can be cleared by software by writ- ing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the waveform generation mode (wgm13:0) bits and compare output mode (com1x1:0) bits. the top and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see ?modes of operation? on page 143 ). a special feature of output compare unit a allows it to define the timer/counter top value (i.e., counter resolution). in addition to the counter resolution, the top value defines the period time for waveforms generated by the waveform generator. figure 4-43 shows a block diagram of the output compare unit. the small ?n? in the register and bit names indicates the device number (n = 1 for timer/counter 1), and the ?x? indicates output compare unit (a/b). the elements of the block diagram that are not directly a part of the output compare unit are gray shaded. figure 4-43. output compare unit, block diagram ocfnx (int.req.) = (16-bit comparator) ocrnx buffer (16-bit register) ocrnxh buf. (8-bit) ocnx temp (8-bit) data bus (8-bit) ocrnxl buf. (8-bit) tcntn (16-bit counter) tcntnh (8-bit) tcntnl (8-bit) comnx1:0 wgmn3:0 ocrnx (16-bit register) ocrnxh (8-bit) ocrnxl (8-bit) waveform generator top bottom 141 4921e?auto?09/09 ata6602/ata6603 the ocr1x register is double buffered when using any of the twelve pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr1x com- pare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the out- put glitch-free. the ocr1x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr1x buffer register, and if double buffering is dis- abled the cpu will access the ocr1x directly. the content of the ocr1x (buffer or compare) register is only changed by a write operation (the timer/counter does not update this register automatically as the tcnt1 and icr1 register). therefore ocr1x is not read via the high byte temporary register (temp). however, it is a good practice to read the low byte first as when accessing other 16-bit registers. writing the ocr1x registers must be done via the temp reg- ister since the compare of all 16 bits is done continuously. the high byte (ocr1xh) has to be written first. when the high byte i/o location is written by the cpu, the temp register will be updated by the value written. then when the low by te (ocr1xl) is written to the lower eight bits, the high byte will be copied into the upper 8-bits of either the ocr1x bu ffer or ocr1x compare register in the same system clock cycle. for more information of how to access the 16-bit registers refer to ?accessing 16-bit registers? on page 133 . 4.14.6.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force output compare (foc1x) bit. forcing compare match will not set the ocf1x flag or reload/clear the timer, but the oc1x pin will be updated as if a real compare match had occurred (the com11:0 bits settings define whether the oc1x pin is set, cleared or toggled). 4.14.6.2 compare match blocking by tcnt1 write all cpu writes to the tcnt1 register will block any compare match that o ccurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr1x to be initialized to the same value as tcnt1 without triggering an inte rrupt when the timer/counter clock is enabled. 4.14.6.3 using the output compare unit since writing tcnt1 in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changing tcnt1 when using any of the output compare channels, independent of whether the timer/counter is running or not. if the value written to tcnt1 equals the ocr1x value, the compare matc h will be missed, resulting in incorrect wave- form generation. do not write the tcnt1 equal to top in pwm modes with variable top values. the compare match for the top will be ignored and the counte r will continue to 0xffff. similarly, do not write the tcnt1 value equal to bottom when the counter is downcounting. the setup of the oc1x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc1x value is to use the force output com- pare (foc1x) strobe bits in normal mode. the oc1x register keeps its value even when changing between waveform generation modes. be aware that the com1x1:0 bits are not doubl e buffered together with the compare value. changing the com1x1:0 bits will take effect immediately. 142 4921e?auto?09/09 ata6602/ata6603 4.14.7 compare match output unit the compare output mode (com1x1:0) bits have two functions. the waveform generator uses the com1x1:0 bits for defining the output compare (oc1x) state at the next compare match. secondly the com1x1:0 bits control the oc1x pin output source. figure 4-44 shows a simplified schematic of the logic affected by the com1x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com1x1:0 bits are shown. when referring to the oc1x state, the reference is for the internal oc1x register, not the oc1x pin. if a system reset occur, the oc1x register is reset to ?0?. figure 4-44. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc1x) from the waveform generator if either of the com1x1:0 bits are set. however, the oc1x pin direction (input or out- put) is still controlled by the data direction register (ddr) for the port pin. the data direction register bit for the oc1x pin (ddr_oc1x) must be set as output before the oc1x value is visi- ble on the pin. the port override function is generally independent of the waveform generation mode, but there are some exceptions. refer to table 4-53 on page 153 , table 4-54 on page 153 and table 4-55 on page 154 for details. the design of the output compare pin logic allows initialization of the oc1x state before the out- put is enabled. note that some com1x1:0 bi t settings are reserved for certain modes of operation (see ?16-bit timer/counter register description? on page 153 ). the com1x1:0 bits have no effect on the input capture unit. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data bus focnx clk i/o 143 4921e?auto?09/09 ata6602/ata6603 4.14.7.1 compare output mode and waveform generation the waveform generator uses the com1x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com1x1:0 = 0 tells the waveform generator that no action on the oc1x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 4-53 on page 153 . for fast pwm mode refer to table 4-54 on page 153 , and for phase correct and phase and frequency correct pwm refer to table 4-55 on page 154 . a change of the com1x1:0 bits st ate will have effect at the first compare matc h after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc1x strobe bits. 4.14.8 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm13:0) and compare output mode (com1x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com1x1:0 bits control whether the pwm out- put generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com1x1:0 bits control whether the output should be set, cleared or toggle at a compare match (see ?compare match output unit? on page 142 ). for detailed timing information refer to ?timer/counter timing diagrams? on page 151 . 4.14.8.1 normal mode the simplest mode of operation is the normal mode (wgm13:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 16-bit value (max = 0xffff) and then restarts from the bottom (0x0000). in normal operation the timer/counter overflow flag (tov1) will be set in the same timer clock cycle as the tcnt1 become s zero. the tov1 flag in this case behaves like a 17th bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov1 flag, the timer resolution can be increased by soft- ware. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the input capture unit is easy to use in normal mode. however, observe that the maximum interval between the external events must not exceed the resolution of the counter. if the interval between events are too long, the timer overflow interrupt or the prescaler must be used to extend the resolution for the capture unit. the output compare units can be used to generat e interrupts at some given time. using the output compare to gene rate waveforms in norm al mode is not recommended, since this will occupy too much of the cpu time. 144 4921e?auto?09/09 ata6602/ata6603 4.14.8.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm13:0 = 4 or 12), the ocr1a or icr1 register are used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt1) matches either the ocr1a (wgm13:0 = 4) or the icr1 (wgm13:0 = 12). the ocr1a or icr1 define the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the opera- tion of counting external events. the timing diagram for the ctc mode is shown in figure 4-45 . the counter value (tcnt1) increases until a compare match occurs with either ocr1a or icr1, and then counter (tcnt1) is cleared. figure 4-45. ctc mode, timing diagram an interrupt can be generated at each time the counter value reaches the top value by either using the ocf1a or icf1 flag according to the register used to define the top value. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. how- ever, changing the top to a value close to bottom when the counter is running with none or a low prescaler value must be done with care since the ctc mode does not have the double buff- ering feature. if the new value written to ocr1a or icr1 is lower than the current value of tcnt1, the counter will miss the co mpare match. the counter will then have to count to its max- imum value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. in many cases this feature is no t desirable. an alternative will th en be to use the fast pwm mode using ocr1a for defining top (w gm13:0 = 15) since the ocr1a then will be doub le buffered. for generating a waveform output in ctc mode, the oc1a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com1a1:0 = 1). the oc1a value will not be visible on the port pin unless the data direction for the pin is set to output (ddr_oc1a = 1). th e waveform generated will have a maximum fre- quency of f oc 1 a = f clk_i/o /2 when ocr1a is set to zero (0x0000). the waveform frequency is defined by the following equation: the n variable represents the prescaler factor (1, 8, 64, 256, or 1024). as for the normal mode of operation, the tov1 flag is set in the same timer clock cycle that the counter counts from max to 0x0000. tcntn ocna (toggle) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 4 period 2 3 (comna1:0 = 1) f ocna f clk_i/o 2 n 1 ocrna + () ?? -------------------------------------------------------- = 145 4921e?auto?09/09 ata6602/ata6603 4.14.8.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm13:0 = 5, 6, 7, 14, or 15) provides a high frequency pwm waveform generation option. the fast pwm differs from the other pwm options by its single-slope operation. the counter counts from bottom to top then restarts from bottom. in non-inverting compare output mode, the output compare (oc1x) is set on the compare match between tcnt1 and ocr1x, and cleared at top. in inverting compare output mode output is cleared on compare match and set at top. due to the single-slope oper- ation, the operating frequency of the fast pwm mode can be twice as high as the phase correct and phase and frequency correct pwm modes that use dual-slope operation. this high fre- quency makes the fast pwm mode well suited for power regulation, rectification, and dac applications. high frequency allows physically sm all sized external com ponents (coils, capaci- tors), hence reduces total system cost. the pwm resolution for fast pwm can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the max- imum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolution in bits can be calculated by using the following equation: in fast pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm13:0 = 5, 6, or 7), the value in icr1 (wgm13:0 = 14), or the value in ocr1a (wgm13:0 = 15). the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 4-46 . the figure shows fast pwm mode when ocr1a or icr1 is us ed to define top. the tcnt1 value is in the timing diagram shown as a histogram for illu strating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x interrupt flag will be set when a compare match occurs. figure 4-46. fast pwm mode, timing diagram r fpwm top 1 + () log 2 () log ---------------------------------- - = tcntn ocrnx/top update and tovn interrupt flag set and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 7 period 2 3 4 5 6 8 ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 146 4921e?auto?09/09 ata6602/ata6603 the timer/counter overflow flag (tov1) is set each time the counter reaches top. in addition the oc1a or icf1 flag is set at the same time r clock cycle as tov1 is set when either ocr1a or icr1 is used for defining the top value. if one of the interrupts are enabled, the interrupt han- dler routine can be used for updating the top and compare values. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1x. note that when using fixed top values the unused bits are masked to zero when any of the ocr1x registers are written. the procedure for updating icr1 differs from updating ocr1a when used for defining the top value. the icr1 register is not double buffered. this means that if icr1 is changed to a low value when the counter is running with none or a low prescaler value, there is a risk that the new icr1 value written is lower than the current va lue of tcnt1. the result will then be that the counter will miss the compare matc h at the top value. the counter will then have to count to the max value (0xffff) and wrap around starting at 0x0000 before the compare match can occur. the ocr1a register however, is double buffered. this feature allows the ocr1a i/o location to be written anytime. when the ocr1a i/o location is written the value written will be put into the ocr1a buffer register. th e ocr1a compare register will th en be updated with the value in the buffer register at the next timer clo ck cycle the tcnt1 matches top. the update is done at the same timer clock cycle as the tcnt 1 is cleared and the tov1 flag is set. using the icr1 register for defining top work s well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. however, if the base pwm frequency is actively change d (by changing the top value), using the ocr1a as top is clearly a better choice due to its double buffer feature. in fast pwm mode, the compare units allow generation of pwm waveforms on the oc1x pins. setting the com1x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com1x1:0 to three (see table on page 153 ). the actual oc1x value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the pwm waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1, and clearing (or setting) the oc1x register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represents special cases when generating a pwm waveform output in the fast pwm mode. if the ocr1x is set equal to bottom (0x0000) the out- put will be a narrow spike for eac h top+1 timer clock cycle. se tting the ocr1x equal to top will result in a const ant high or low output (depending on the polarity of the output set by the com1x1:0 bits). f ocnxpwm f clk_i/o n 1 top + () ? ------------------------------------- = 147 4921e?auto?09/09 ata6602/ata6603 a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by set- ting oc1a to toggle its logical level on each compare match (com1a1:0 = 1). this applies only if ocr1a is used to define the top value (wgm 13:0 = 15). the wave form generated will have a maximum frequency of f oc 1 a = f clk_i/o /2 when ocr1a is set to zero (0x0000). this feature is similar to the oc1a toggle in ctc mode, except the double buffer feature of the output com- pare unit is enabled in the fast pwm mode. 4.14.8.4 phase correct pwm mode the phase correct pulse width modulation or phase correct pwm mode (wgm13:0 = 1, 2, 3, 10, or 11) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is, like the phase and frequency correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feat ure of the dual-slope pwm modes, these modes are preferred for motor control applications. the pwm resolution for the phase correct pwm mode can be fixed to 8-, 9-, or 10-bit, or defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1a set to max). the pwm resolu- tion in bits can be calculated by using the following equation: in phase correct pwm mode the counter is incremented until the counter value matches either one of the fixed values 0x00ff, 0x01ff, or 0x03ff (wgm13:0 = 1, 2, or 3), the value in icr1 (wgm13:0 = 10), or the value in ocr1a (wgm13:0 = 11). the counter has then reached the top and changes the count direct ion. the tcnt1 value will be equa l to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 4-47 on page 148 . the figure shows phase correct pwm mode w hen ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x interrupt flag will be set when a compare match occurs. r pcpwm top 1 + () log 2 () log ---------------------------------- - = 148 4921e?auto?09/09 ata6602/ata6603 figure 4-47. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov1) is set each time the counter reaches bottom. when either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag is set accord- ingly at the same timer clock cycle as the ocr1x registers are updated with the double buffer value (at top). the interrupt flags can be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will never occur between the tcnt1 and the ocr1x. note that when using fixed top values, the unus ed bits are masked to zero when any of the ocr1x registers are written. as the third period shown in figure 4-47 illustrates, changing the top actively while the timer/counter is running in the phase correct mode can result in an unsymmetrical output. the reason for this can be found in the time of update of the ocr1x reg- ister. since the ocr1x update occurs at top, the pwm period starts and ends at top. this implies that the length of the falling slope is determined by the previous top value, while the length of the rising slope is determined by th e new top value. when these two values differ the two slopes of the period will differ in length. the difference in length gives the unsymmetrical result on the output. it is recommended to use the phase and frequency correct mode instead of the phase correct mode when changing the top value while the timer/counter is running. when using a static top value there are practically no differences between the two modes of operation. in phase correct pwm mode, the compare units allow generation of pwm waveforms on the oc1x pins. setting the com1x1:0 bits to tw o will produce a non-inverte d pwm and an inverted pwm output can be generated by setting the com1x1:0 to thre e. the actual oc1x value will only be visible on the port pin if the data direct ion for the port pin is set as output (ddr_oc1x). the pwm waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1 when the counte r increments, and clearing (or setting) the oc1x register at compare match between ocr1x and tcnt1 when the counter decrements. ocrnx/top update and ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tovn interrupt flag set (interrupt on bottom) tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) 149 4921e?auto?09/09 ata6602/ata6603 the pwm frequency for the output when using phase correct pwm can be calculated by the fol- lowing equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). the extreme values for the ocr1x register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr1x is set equal to bottom the output will be continuously low and if set equal to top the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. if ocr1a is used to define the top value (wgm13:0 = 11) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 4.14.8.5 phase and frequency correct pwm mode the phase and frequency correct pulse width modulation, or phase and frequency correct pwm mode (wgm13:0 = 8 or 9) provides a high reso lution phase and frequency correct pwm wave- form generation option. the phase and frequency correct pwm mode is, like the phase correct pwm mode, based on a dual-slope operation. the counter counts repeatedly from bottom (0x0000) to top and then from top to bottom. in non-inverting compare output mode, the output compare (oc1x) is cleared on the compare match between tcnt1 and ocr1x while upcounting, and set on the compare match while downcounting. in inverting compare output mode, the operation is inverted. the dual-slope operation gives a lower maximum operation fre- quency compared to the single-slope operation. howe ver, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor control applications. the main difference between the phase correct, and the phase and frequency correct pwm mode is the time the ocr1x register is updated by the ocr1x buffer register (see figure 4-47 on page 148 and figure 4-48 on page 150 ). the pwm resolution for the phase and frequency correct pwm mode can be defined by either icr1 or ocr1a. the minimum resolution allowed is 2-bit (icr1 or ocr1a set to 0x0003), and the maximum resolution is 16-bit (icr1 or ocr1 a set to max). the pwm resolution in bits can be calculated using the following equation: in phase and frequency correct pwm mode the counter is incremented until the counter value matches either the value in icr1 (wgm13:0 = 8), or the value in ocr1a (wgm13:0 = 9). the counter has then reac hed the top and ch anges the count di rection. the tcnt1 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct and frequency correct pwm mode is shown on figure 4-48 on page 150 . the figure shows phase and fre- quency correct pwm mode when ocr1a or icr1 is used to define top. the tcnt1 value is in the timing diagram shown as a histogram for il lustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt1 slopes represent compare matches between ocr1x and tcnt1. the oc1x interrupt flag will be set when a compare match occurs. f ocnxpcpwm f clk_i/o 2 ntop ?? --------------------------------- = r pfcpwm top 1 + () log 2 () log ---------------------------------- - = 150 4921e?auto?09/09 ata6602/ata6603 figure 4-48. phase and frequency correct pwm mode, timing diagram the timer/counter overflow flag (tov1) is set at the same timer clock cycle as the ocr1x registers are updated with the double buffer value (at bottom). when either ocr1a or icr1 is used for defining the top value, the oc1a or icf1 flag set when tcnt1 has reached top. the interrupt flags can then be used to generate an interrupt each time the counter reaches the top or bottom value. when changing the top value the program must ensure that the new top value is higher or equal to the value of all of the compare registers. if the top value is lower than any of the compare registers, a compare match will neve r occur between the tcnt1 and the ocr1x. as figure 4-48 shows the output generated is, in contrast to the phase correct mode, symmetri- cal in all periods. since the ocr1x registers are updated at bottom, the length of the rising and the falling slopes will always be equal. this gives symmetrical output pulses and is therefore frequency correct. using the icr1 register for defining top work s well when using fixed top values. by using icr1, the ocr1a register is free to be used for generating a pwm output on oc1a. however, if the base pwm frequency is actively changed by changing the top value, using the ocr1a as top is clearly a better choice due to its double buffer feature. in phase and frequency correct pwm mode, the compare units allow generation of pwm wave- forms on the oc1x pins. settin g the com1x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com1x1:0 to three (see table on page 154 ). the actual oc1x value will only be visible on the port pin if the data direction for the port pin is set as output (ddr_oc1x). the pwm waveform is generated by setting (or clearing) the oc1x register at the compare match between ocr1x and tcnt1 when the counter incre- ments, and clearing (or setting) the oc1x register at compare match between ocr1x and tcnt1 when the counter decrements. the pw m frequency for the output when using phase and frequency correct pwm can be calculated by the following equation: the n variable represents the prescaler divider (1, 8, 64, 256, or 1024). ocrnx/top updateand tovn interrupt flag set (interrupt on bottom) ocna interrupt flag set or icfn interrupt flag set (interrupt on top) 1 2 3 4 tcntn period ocnx ocnx (comnx1:0 = 2) (comnx1:0 = 3) f ocnxpfcpwm f clk_i/o 2 ntop ?? --------------------------------- = 151 4921e?auto?09/09 ata6602/ata6603 the extreme values for the ocr1x register represents special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr1x is set equal to bottom the output will be continuously low and if set equal to top th e output will be set to high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. if ocr1a is used to define the top value (wgm13:0 = 9) and com1a1:0 = 1, the oc1a output will toggle with a 50% duty cycle. 4.14.9 timer/counter timing diagrams the timer/counter is a synchronous design and the timer clock (clk t1 ) is therefore shown as a clock enable signal in the following figures. the figures include information on when interrupt flags are set, and when the ocr1x register is updated with the ocr1x buffer value (only for modes utilizing doub le buffering). figure 4-49 shows a timing diagram for the setting of ocf1x. figure 4-49. timer/counter timing diagram, setting of ocf1x, no prescaling figure 4-50 shows the same timing data, but with the prescaler enabled. figure 4-50. timer/counter timing diagram, setting of ocf1x, with prescaler (f clk_i/o /8) clktn (clk i/o /1) ocfnx clk i/o ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clktn (clk i/o /8) 152 4921e?auto?09/09 ata6602/ata6603 figure 4-51 shows the count sequence close to top in various modes. when using phase and frequency correct pwm mode the ocr1x register is updated at bottom. the timing diagrams will be the same, but top should be replaced by bottom, top-1 by bottom+1 and so on. the same renaming applies for modes that set the tov1 flag at bottom. figure 4-51. timer/counter timing diagram, no prescaling figure 4-52 shows the same timing data, but with the prescaler enabled. figure 4-52. timer/counter timing dia gram, with prescaler (f clk_i/o /8) tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk tn (clk i/o /1) clk i/o tovn (fpwm) and icfn (if used as top) ocrnx (update at top) tcntn (ctc and fpwm) tcntn (pc and pfc pwm) top - 1 top top - 1 top - 2 old ocrnx value new ocrnx value top - 1 top bottom bottom + 1 clk i/o clk tn (clk i/o /8) 153 4921e?auto?09/09 ata6602/ata6603 4.14.10 16-bit timer/counter register description 4.14.10.1 timer/counter1 control register a ? tccr1a ? bit 7:6 ? com1a1:0: compare output mode for channel a ? bit 5:4 ? com1b1:0: compare output mode for channel b the com1a1:0 and com1b1:0 control the output compare pins (oc1a and oc1b respec- tively) behavior. if one or both of the com1a1:0 bits are written to one, the oc1a output overrides the normal port functionality of the i/o pin it is connected to. if one or both of the com1b1:0 bit are written to one, the oc1b outp ut overrides the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit corre- sponding to the oc1a or oc1b pin must be set in order to enable the output driver. when the oc1a or oc1b is connected to the pin, the function of the com1x1:0 bits is dependent of the wgm13:0 bits setting. table 4-53 shows the com1x1:0 bit functionality when the wgm13:0 bits are set to a normal or a ctc mode (non-pwm). table 4-54 shows the com1x1:0 bit functionality when the wgm13:0 bits are set to the fast pwm mode. note: 1. a special case occurs when ocr1a/oc r1b equals top and com1a1/com1b1 is set. in this case the compare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 145 for more details. bit 76543210 com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 tccr1a read/write r/w r/w r/w r/w r r r/w r/w initial value00000000 table 4-53. compare output mode, non-pwm com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 0 1 toggle oc1a/oc1b on compare match. 10 clear oc1a/oc1b on compare match (set output to low level). 11 set oc1a/oc1b on compare match (set output to high level). table 4-54. compare output mode, fast pwm (1) com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 01 wgm13:0 = 14 or 15: toggle oc1a on compare match, oc1b disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b disconnected. 10 clear oc1a/oc1b on compare match, set oc1a/oc1b at top 11 set oc1a/oc1b on compare match, clear oc1a/oc1b at top 154 4921e?auto?09/09 ata6602/ata6603 table 4-55 shows the com1x1:0 bit functionality when the wgm13:0 bits are set to the phase correct or the phase and frequency correct, pwm mode. note: 1. a special case occurs when ocr1a/oc r1b equals top and com1a1/com1b1 is set. see ?phase correct pwm mode? on page 147 for more details. ? bit 1:0 ? wgm11:0: waveform generation mode combined with the wgm13:2 bits found in t he tccr1b register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of waveform generation to be used (see table 4-56 on page 155 ). modes of operation supported by the timer/counter unit are: norma l mode (counter), clear timer on compare match (ctc) mode, and three types of pulse width modulation (pwm) modes (see ?modes of operation? on page 143 ). table 4-55. compare output mode, phase correct and phase and frequency correct pwm (1) com1a1/com1b1 com1a0/com1b0 description 0 0 normal port operation, oc1a/oc1b disconnected. 01 wgm13:0 = 8, 9, 10 or 11: toggle oc1a on compare match, oc1b disconnected (normal port operation). for all other wgm1 settings, normal port operation, oc1a/oc1b disconnected. 10 clear oc1a/oc1b on compare match when up-counting. set oc1a/oc1b on compare match when downcounting. 11 set oc1a/oc1b on compare match when up-counting. clear oc1a/oc1b on compare match when downcounting. 155 4921e?auto?09/09 ata6602/ata6603 note: 1. the ctc1 and pwm11:0 bit definition names are obsolete. use the wgm12:0 definitions. however, the functionality and location of these bits are compatible with previous versions of the timer. 4.14.10.2 timer/counter1 control register b ? tccr1b ? bit 7 ? icnc1: input capture noise canceler setting this bit (to one) activates the input ca pture noise canceler. when the noise canceler is activated, the input from the input capture pin (icp1) is filtered. the filter function requires four successive equal valued samples of the icp1 pin for changing its output. the input capture is therefore delayed by four oscillator cycles when the noise canceler is enabled. ? bit 6 ? ices1: input capture edge select this bit selects which edge on the input capture pin (icp1) that is used to trigger a capture event. when the ices1 bit is written to zero, a falling (negative) edge is used as trigger, and when the ices1 bit is written to one, a risi ng (positive) edge w ill trigger the capture. when a capture is triggered according to the ices1 setting, the counter value is copied into the input capture register (icr1 ). the event will also set the input capture flag (icf1), and this can be used to cause an input capture interrupt, if this interrupt is enabled. when the icr1 is used as top value (see description of the wgm13:0 bits located in the tccr1a and the tccr1b register), the icp1 is disconnected and consequently the input capture function is disabled. table 4-56. waveform generation mode bit description (1) mode wgm13 wgm12 (ctc1) wgm11 (pwm11) wgm10 (pwm10) timer/counter mode of operation top update of ocr1 x at tov1 flag set on 0 0 0 0 0 normal 0xffff immediate max 1 0 0 0 1 pwm, phase correct, 8-bit 0x00ff top bottom 2 0 0 1 0 pwm, phase correct, 9-bit 0x01ff top bottom 3 0 0 1 1 pwm, phase correct, 10-bit 0x03ff top bottom 4 0 1 0 0 ctc ocr1a immediate max 5 0 1 0 1 fast pwm, 8-bit 0x00ff top top 6 0 1 1 0 fast pwm, 9-bit 0x01ff top top 7 0 1 1 1 fast pwm, 10-bit 0x03ff top top 81000 pwm, phase and frequency correct icr1 bottom bottom 91001 pwm, phase and frequency correct ocr1a bottom bottom 10 1 0 1 0 pwm, phase correct icr1 top bottom 11 1 0 1 1 pwm, phase correct ocr1a top bottom 12 1 1 0 0 ctc icr1 immediate max 13 1 1 0 1 (reserved) ? ? ? 14 1 1 1 0 fast pwm icr1 top top 15 1 1 1 1 fast pwm ocr1a top top bit 7654 3210 icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 tccr1b read/write r/w r/w r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 156 4921e?auto?09/09 ata6602/ata6603 ? bit 5 ? reserved bit this bit is reserved for future use. for ensuring compatibility with future devices, this bit must be written to zero when tccr1b is written. ? bit 4:3 ? wgm13:2: waveform generation mode see tccr1a register description. ? bit 2:0 ? cs12:0: clock select the three clock select bits select the clock source to be used by the timer/counter, see figure 4-49 on page 151 and figure 4-50 on page 151 . if external pin modes are used for the timer/counter1, transitions on the t1 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 4.14.10.3 timer/counter1 control register c ? tccr1c ? bit 7 ? foc1a: force output compare for channel a ? bit 6 ? foc1b: force output compare for channel b the foc1a/foc1b bits are only active when the wgm13:0 bits specifies a non-pwm mode. however, for ensuring comp atibility with future devices, these bits must be set to zero when tccr1a is written when operating in a pwm mode. when writing a logical one to the foc1a/foc1b bit, an immediate compare match is forced on the waveform generation unit. the oc1a/oc1b output is changed according to its com1x1:0 bits setting. note that the foc1a/foc1b bits are implemented as strobes. therefore it is the value present in the com1x1:0 bits that determine the effect of the forced compare. a foc1a/foc1b strobe will not generate any inte rrupt nor will it clea r the timer in clear timer on compare match (ctc) mode using ocr1a as top. the foc1a/foc1b bits are always read as zero. table 4-57. clock select bit description cs12 cs11 cs10 description 0 0 0 no clock source (timer/counter stopped). 001clk i/o /1 (no prescaling) 010clk i/o /8 (from prescaler) 011clk i/o /64 (from prescaler) 100clk i/o /256 (from prescaler) 101clk i/o /1024 (from prescaler) 1 1 0 external clock source on t1 pin. clock on falling edge. 1 1 1 external clock source on t1 pin. clock on rising edge. bit 7654 3210 foc1a foc1b ? ? ? ? ? ? tccr1c read/write r/w r/w r r r r r r initial value0000 0000 157 4921e?auto?09/09 ata6602/ata6603 4.14.10.4 timer/counter1 ? tcnt1h and tcnt1l the two timer/counter i/o locations (tcnt1h and tcnt1l , combined tcnt1) give direct access, both for read and for write operations, to the timer/counter unit 16-bit counter. to ensure that both the high and low bytes are read and written simultaneously when the cpu accesses these registers, the access is perfo rmed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers see ?accessing 16-bit registers? on page 133 . modifying the counter (tcnt1) while the counte r is running introduces a risk of missing a com- pare match between tcnt1 and one of the ocr1x registers. writing to the tcnt1 register blocks (removes) the compare match on the following timer clock for all compare units. 4.14.10.5 output compare register 1 a ? ocr1ah and ocr1al 4.14.10.6 output compare register 1 b ? ocr1bh and ocr1bl the output compare registers contain a 16-bit value that is continuously compared with the counter value (tcnt1). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc1x pin. the output compare registers are 16-bit in size. to ensure that both the high and low bytes are written simultaneously when the cp u writes to these registers, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers (see ?accessing 16-bit registers? on page 133 ). bit 76543210 tcnt1[15:8] tcnt1h tcnt1[7:0] tcnt1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1a[15:8] ocr1ah ocr1a[7:0] ocr1al read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr1b[15:8] ocr1bh ocr1b[7:0] ocr1bl read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 158 4921e?auto?09/09 ata6602/ata6603 4.14.10.7 input capture register 1 ? icr1h and icr1l the input capture is updated with the counter (tcnt1) value each time an event occurs on the icp1 pin (or optionally on the analog comparator output for timer/counter1). the input capture can be used for defining the counter top value. the input capture register is 16-bit in size. to ensure that both the high and low bytes are read simultaneously when the cpu accesses these regi sters, the access is performed using an 8-bit temporary high byte register (temp). this temporary register is shared by all the other 16-bit registers (see ?accessing 16-bit registers? on page 133 ). 4.14.10.8 timer/counter1 interrupt mask register ? timsk1 ? bit 7, 6 ? res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bit 5 ? icie1: timer/counter1, input capture interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 input capture in terrupt is enabled. the corresponding inter- rupt vector (see ?interrupts? on page 77 ) is executed when the icf1 flag, located in tifr1, is set. ? bit 4, 3 ? res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bit 2 ? ocie1b: timer/counter1, output compare b match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare b match interrupt is enabled. the corre- sponding interrupt vector (see ?interrupts? on page 77 ) is executed when the ocf1b flag, located in tifr1, is set. ? bit 1 ? ocie1a: timer/counter1, output compare a match interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 output compare a match interrupt is enabled. the corre- sponding interrupt vector (see ?interrupts? on page 77 ) is executed when the ocf1a flag, located in tifr1, is set. ? bit 0 ? toie1: timer/counter1, overflow interrupt enable when this bit is written to one, and the i-flag in the status register is set (interrupts globally enabled), the timer/counter1 overflow interrupt is enabled. the corresponding interrupt vector (see ?watchdog timer? on page 72 ) is executed when the tov1 flag, located in tifr1, is set. bit 76543210 icr1[15:8] icr1h icr1[7:0] icr1l read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 bit 76543210 ? ? icie1 ? ? ocie1b ocie1a toie1 timsk1 read/write r r r/w r r r/w r/w r/w initial value00000000 159 4921e?auto?09/09 ata6602/ata6603 4.14.10.9 timer/counter1 interrupt flag register ? tifr1 ? bit 7, 6 ? res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bit 5 ? icf1: timer/counter1, input capture flag this flag is set when a capture event occurs on the icp1 pin. when the input capture reg- ister (icr1) is set by the wgm13:0 to be used as the top value, the icf1 flag is set when the counter reaches the top value. icf1 is automatically cleared when the input capture interrupt vector is executed. alterna- tively, icf1 can be cleared by writing a logic one to its bit location. ? bit 4, 3 ? res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bit 2 ? ocf1b: timer/counter1, output compare b match flag this flag is set in the timer clock cycle after the counter (tcnt1) value matches the output compare register b (ocr1b). note that a forced output compare (foc 1b) strobe will not set the ocf1b flag. ocf1b is automatically cleared when the output compare match b interrupt vector is exe- cuted. alternatively, ocf1b can be cleared by writing a logic one to its bit location. ? bit 1 ? ocf1a: timer/counter1, output compare a match flag this flag is set in the timer clock cycle after the counter (tcnt1) value matches the output compare register a (ocr1a). note that a forced output compare (foc 1a) strobe will not set the ocf1a flag. ocf1a is automatically cleared when the output compare match a interrupt vector is exe- cuted. alternatively, ocf1a can be cleared by writing a logic one to its bit location. ? bit 0 ? tov1: timer/counter1, overflow flag the setting of this flag is dependent of the wgm13:0 bits setting. in normal and ctc modes, the tov1 flag is set when the timer overflows. refer to table 4-56 on page 155 for the tov1 flag behavior when using another wgm13:0 bit setting. tov1 is automatically cleared when the timer/counter1 overflow interrupt vector is exe- cuted. alternatively, tov1 can be cleared by writing a logic one to its bit location. bit 76543210 ??icf1??ocf1bocf1atov1tifr1 read/write r r r/w r r r/w r/w r/w initial value00000000 160 4921e?auto?09/09 ata6602/ata6603 4.15 8-bit timer/counter2 with pwm and asynchronous operation timer/counter2 is a general purpose, single channel, 8-bit timer/counter module. the main features are: ? single channel counter ? clear timer on compare match (auto reload) ? glitch-free, phase correct pu lse width modulator (pwm) ? frequency generator ? 10-bit clock prescaler ? overflow and compare ma tch interrupt sources (tov2, ocf2a and ocf2b) ? allows clocking from external 32 khz wa tch crystal independent of the i/o clock 4.15.1 overview a simplified block diagram of the 8-bit timer/counter is shown in figure 4-53 . the device-spe- cific i/o register and bit locations are listed in the ?8-bit timer/counter register description? on page 172 . the prtim2 bit in ?power reduction register - prr? on page 64 must be written to zero to enable timer/counter2 module. figure 4-53. 8-bit timer/counter block diagram timer/counter data bus ocrna ocrnb = = tcntn waveform generation waveform generation ocna ocnb = fixed top value control logic = 0 top bottom count clear direction tovn (int.req.) ocna (int.req.) ocnb (int.req.) tccrna tccrnb clk tn prescaler t/c oscillator clk i/o tosc1 tosc2 161 4921e?auto?09/09 ata6602/ata6603 4.15.1.1 registers the timer/counter (tcnt2) and output compare register (ocr2a and ocr2b) are 8-bit reg- isters. interrupt request (shorten as int.req.) signals are all visible in the timer interrupt flag register (tifr2). all interrupts are individua lly masked with the timer interrupt mask register (timsk2). tifr2 and timsk2 are not shown in the figure. the timer/counter can be clocked internally, via the prescaler, or asynchronously clocked from the tosc1/2 pins, as detailed later in this section. the asynchronous operation is controlled by the asynchronous status regist er (assr). the clock select lo gic block controls which clock source he timer/counter uses to increment (or decrement) its value. the timer/counter is inac- tive when no clock source is selected. the output from the clock select logic is referred to as the timer clock (clk t2 ). the double buffered output compare register (ocr2a and ocr2b) are compared with the timer/counter value at all times. the result of the compare can be used by the waveform gen- erator to generate a pwm or variable frequency output on the output compare pins (oc2a and oc2b). see ?output compare unit? on page 163 for details. the comp are match event will also set the compare flag (ocf2a or ocf2b) which can be used to generate an output compare interrupt request. 4.15.1.2 definitions many register and bit references in this document are written in general form. a lower case ?n? replaces the timer/counter number, in this case 2. however, when using the register or bit defines in a program, the precise form must be used, i.e., tcnt2 for accessing timer/counter2 counter value and so on. the definitions below are also used extensively throughout the section. 4.15.2 timer/counter clock sources the timer/counter can be clocked by an internal synchronous or an external asynchronous clock source. the clock source clk t2 is by default equal to the mcu clock, clk i/o . when the as2 bit in the assr register is written to logic one, the clock source is taken from the timer/counter oscillator connected to tosc1 and tosc2. fo r details on asynchro nous operation (see ?asyn- chronous status register ? assr? on page 179 ). for details on clock sources and prescaler, see ?timer/counter prescaler? on page 181 . bottom the counter reaches the bottom when it becomes zero (0x00). max the counter reaches its maximum wh en it becomes 0xff (decimal 255). top the counter reaches the top when it becomes equal to the highest value in the count sequence. the top value can be assigned to be the fixed value 0xff (max) or the value stored in the ocr2a register. the assignment is dependent on the mode of operation. 162 4921e?auto?09/09 ata6602/ata6603 4.15.3 counter unit the main part of the 8-bit timer/counter is the programmable bi-directional counter unit. figure 4-54 shows a block diagram of the counter and its surrounding environment. figure 4-54. counter unit block diagram signal description (internal signals): count increment or decrement tcnt2 by 1. direction selects between increment and decrement. clear clear tcnt2 (set all bits to zero). clk tn timer/counter clock, referred to as clk t2 in the following. top signalizes that tcnt2 has reached maximum value. bottom signalizes that tcnt2 has reached minimum value (zero). depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk t2 ). clk t2 can be generated from an external or internal clock source, selected by the clock select bits (cs22:0). w hen no clock source is selected (cs22:0 = 0) the timer is stopped. however, the tcnt2 value can be accessed by the cpu, regardless of whether clk t2 is present or not. a cpu write overrides (has priority over) all counter clear or count operations. the counting sequence is determined by the setting of the wgm21 and wgm20 bits located in the timer/counter control register (tccr2a) and the wgm22 located in the timer/counter control register b (tccr2b). there are clos e connections between how the counter behaves (counts) and how waveforms are generated on the output compare outputs oc2a and oc2b. for more details about advanced counting sequences and waveform generation (see ?modes of operation? on page 166 ). the timer/counter overflow flag (tov2) is set according to the mode of operation selected by the wgm22:0 bits. tov2 can be used for generating a cpu interrupt. data b u s tcntn control logic count tovn (int.req.) top bottom direction clear tosc1 t/c oscillator tosc2 prescaler clk i/o clk tn 163 4921e?auto?09/09 ata6602/ata6603 4.15.4 output compare unit the 8-bit comparator continuously compares tcnt2 with the output compare register (ocr2a and ocr2b). whenever tcnt2 equals ocr2a or ocr2b, the comparator signals a match. a match will set the output compare flag (ocf2a or ocf2b) at the next timer clock cycle. if the corresponding interrupt is enabled, the output compare flag generates an output compare interrupt. the output compare flag is automatically cleared when the interrupt is exe- cuted. alternatively, the output compare flag can be cleared by software by writing a logical one to its i/o bit location. the waveform generator uses the match signal to generate an output according to operating mode set by the wgm22:0 bits and compare output mode (com2x1:0) bits. the max and bottom signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation (see ?modes of operation? on page 166 ). figure 4-55 shows a block diagram of the output compare unit. figure 4-55. output compare unit, block diagram the ocr2x register is double buffered when using any of the pulse width modulation (pwm) modes. for the normal and clear timer on compare (ctc) modes of operation, the double buffering is disabled. the double buffering synchronizes the update of the ocr2x compare register to either top or bottom of the counting sequence. the synchronization prevents the occurrence of odd-length, non-symmetrical pwm pulses, thereby making the output glitch-free. the ocr2x register access may seem complex, but this is not case. when the double buffering is enabled, the cpu has access to the ocr2x buffer register, and if double buffering is dis- abled the cpu will access the ocr2x directly. 4.15.4.1 force output compare in non-pwm waveform generation modes, the match output of the comparator can be forced by writing a one to the force outp ut compare (foc2x) bit. forci ng compare match will not set the ocf2x flag or reload/clear the timer, but the oc2x pin will be updated as if a real compare match had occurred (the com2x1:0 bits settings de fine whether the oc2x pin is set, cleared or toggled). ocfnx (int.req.) = (8-bit comparator) ocrnx ocnx data bus tcntn wgmn1:0 waveform generator top focn comnx1:0 bottom 164 4921e?auto?09/09 ata6602/ata6603 4.15.4.2 compare match blocking by tcnt2 write all cpu write operations to the tcnt2 register will block any compare matc h that occurs in the next timer clock cycle, even when the timer is stopped. this feature allows ocr2x to be initial- ized to the same value as tcnt2 without triggering an interrupt when the timer/counter clock is enabled. 4.15.4.3 using the output compare unit since writing tcnt2 in any mode of operation will block all comp are matches for one timer clock cycle, there are risks involved when changing tcnt2 when using the output compare channel, independently of whether the timer/counter is running or not. if the value written to tcnt2 equals the ocr2x value, the compare match will be missed, resulting in incorrect waveform generation. similarly, do not write the tcnt2 value equal to bottom when the counter is downcounting. the setup of the oc2x should be performed before setting the data direction register for the port pin to output. the easiest way of setting the oc2x value is to use the force output com- pare (foc2x) strobe bit in normal mode. the oc2x register keeps its value even when changing between waveform generation modes. be aware that the com2x1:0 bits are not doubl e buffered together with the compare value. changing the com2x1:0 bits will take effect immediately. 4.15.5 compare match output unit the compare output mode (com2x1:0) bits have two functions. the waveform generator uses the com2x1:0 bits for defining the output compare (oc2x) state at the next compare match. also, the com2x1:0 bits control the oc2x pin output source. figure 4-56 on page 165 shows a simplified schematic of the logic affected by the com2x1:0 bit setting. the i/o registers, i/o bits, and i/o pins in the figure are shown in bold. only the parts of the general i/o port control registers (ddr and port) that are affected by the com2x1:0 bits are shown. when referring to the oc2x state, the reference is for t he internal oc2x register, not the oc2x pin. 165 4921e?auto?09/09 ata6602/ata6603 figure 4-56. compare match output unit, schematic the general i/o port function is overridden by the output compare (oc2x) from the waveform generator if either of the com2x1:0 bits are set. however, the oc2x pin direction (input or out- put) is still controlled by the da ta direction register (ddr) for th e port pin. the data direction register bit for the oc2x pin (ddr_oc2x) must be set as output before the oc2x value is visi- ble on the pin. the port override function is independent of the waveform generation mode. the design of the output compare pin logic allows initialization of the oc2x state before the out- put is enabled. note that some com2x1:0 bi t settings are reserved for certain modes of operation (see ?8-bit timer/counter register description? on page 172 ). 4.15.5.1 compare output mode and waveform generation the waveform generator uses the com2x1:0 bits differently in normal, ctc, and pwm modes. for all modes, setting the com2x1:0 = 0 tells the waveform generator that no action on the oc2x register is to be performed on the next compare match. for compare output actions in the non-pwm modes refer to table 4-61 on page 173 . for fast pwm mode, refer to table 4-62 on page 173 , and for phase correct pwm refer to table 4-63 on page 174 . a change of the com2x1:0 bits st ate will have effect at the first compare matc h after the bits are written. for non-pwm modes, the action can be forced to have immediate effect by using the foc2x strobe bits. port ddr dq dq ocnx pin ocnx dq waveform generator comnx1 comnx0 0 1 data bus focnx clk i/o 166 4921e?auto?09/09 ata6602/ata6603 4.15.6 modes of operation the mode of operation, i.e., the behavior of the timer/counter and the output compare pins, is defined by the combination of the waveform generation mode (wgm22:0) and compare output mode (com2x1:0) bits. the compare output mode bits do not affect the counting sequence, while the waveform generation mode bits do. the com2x1:0 bits control whether the pwm out- put generated should be inverted or not (inverted or non-inverted pwm). for non-pwm modes the com2x1:0 bits control whether the output should be set, cleared, or toggled at a compare match (see ?compare match output unit? on page 164 ). for detailed timing information refer to ?timer/counter timing diagrams? on page 170 . 4.15.6.1 normal mode the simplest mode of operation is the normal mode (wgm22:0 = 0). in this mode the counting direction is always up (incrementing), and no counter clear is performed. the counter simply overruns when it passes its maximum 8-bit value (top = 0xff) and then restarts from the bot- tom (0x00). in normal o peration the timer/counter overflow flag (tov2) will be set in the same timer clock cycle as the tcnt2 becomes zero. the tov2 flag in this case behaves like a ninth bit, except that it is only set, not cleared. however, combined with the timer overflow interrupt that automatically clears the tov2 flag, the timer resolution can be increased by software. there are no special cases to consider in the normal mode, a new counter value can be written anytime. the output compare unit can be used to generate interrupts at some given time. using the out- put compare to generate waveforms in normal mode is not recommended, since this will occupy too much of the cpu time. 4.15.6.2 clear timer on compare match (ctc) mode in clear timer on compare or ctc mode (wgm 22:0 = 2), the ocr2a register is used to manipulate the counter resolution. in ctc mode the counter is cleared to zero when the counter value (tcnt2) matches the ocr2a. the ocr2a defines the top value for the counter, hence also its resolution. this mode allows greater control of the compare match output frequency. it also simplifies the operation of counting external events. the timing diagram for the ctc mode is shown in figure 4-57 . the counter value (tcnt2) increases until a compare match occurs between tcnt2 and ocr2a, and then counter (tcnt2) is cleared. figure 4-57. ctc mode, timing diagram tcntn ocn (toggle) ocnx interrupt flag set 1 4 period 2 3 (comnx1:0 = 1) 167 4921e?auto?09/09 ata6602/ata6603 an interrupt can be generated each time the counter value reaches the top value by using the ocf2a flag. if the interrupt is enabled, the interrupt handler routine can be used for updating the top value. however, changing top to a va lue close to bottom when the counter is run- ning with none or a low prescaler value must be done with care since the ctc mode does not have the double buffering feature. if the new value written to ocr2a is lower than the current value of tcnt2, the counter will miss the compar e match. the counter will then have to count to its maximum value (0xff) and wrap around starting at 0x00 before the compare match can occur. for generating a waveform output in ctc mode, the oc2a output can be set to toggle its logical level on each compare match by setting the compare output mode bits to toggle mode (com2a1:0 = 1). the oc2a value will not be visible on the port pin unless the data direction for the pin is set to output. the wavefo rm generated will have a maximum frequency of f oc2a = f clk_i/o /2 when ocr2a is set to zero (0x00). the waveform frequency is defined by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). as for the normal mode of operation, the tov2 flag is set in the same timer clock cycle that the counter counts from max to 0x00. 4.15.6.3 fast pwm mode the fast pulse width modulation or fast pwm mode (wgm22:0 = 3 or 7) provides a high fre- quency pwm waveform generation option. the fast pwm differs from the other pwm option by its single-slope operation. the counter counts from bottom to top then restarts from bot- tom. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7. in non-inverting compare output mode, the output compare (oc2x) is cleared on the compare match between tcnt2 and ocr2x, and set at bottom. in inverting compare output mode, the output is set on compare match and cleared at bottom. due to the single-slope operation, the operating frequency of the fast pwm mode can be twice as high as the phase correct pwm mode that uses dual-slope operation. this high frequency makes the fast pwm mode well suited for power regulation, rectification, and dac app lications. high frequency a llows physically small sized external components (coils, capacitors), and therefore reduces total system cost. in fast pwm mode, the counter is incremented until the counter value matches the top value. the counter is then cleared at the following timer clock cycle. the timing diagram for the fast pwm mode is shown in figure 4-58 on page 168 . the tcnt2 value is in the timing diagram shown as a histogram for illustrating the single-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 slopes represent compare matches between ocr2x and tcnt2. f ocnx f clk_i/o 2 n 1 ocrnx + () ?? ------------------------------------------------------- = 168 4921e?auto?09/09 ata6602/ata6603 figure 4-58. fast pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches top. if the inter- rupt is enabled, the interrupt handler routine can be used for updating the compare value. in fast pwm mode, the compare unit allows generation of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two will produce a non-inverted pwm and an inverted pwm output can be generated by setting the com2x1:0 to three. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7 (see table 4-59 on page 172 ). the actual oc2x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm wave- form is generated by setting (or clearing) the oc2x register at the compare match between ocr2x and tcnt2, and clearing (or setting) the oc2x register at the timer clock cycle the counter is cleared (changes from top to bottom). the pwm frequency for the output can be calculated by the following equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the fast pwm mode. if the ocr2a is set equal to bottom, the output will be a narrow spike for each max+1 timer clock cycle. setting the ocr2a equal to max will result in a constantly high or low output (depending on the polarity of the output set by the com2a1:0 bits.) a frequency (with 50% duty cycle) waveform output in fast pwm mode can be achieved by set- ting oc2x to toggle its logical level on each compare match (com2x1:0 = 1). the waveform generated will have a ma ximum frequency of f oc2 = f clk_i/o /2 when ocr2a is set to zero. this fea- ture is similar to the oc2a toggle in ctc mode, except the double buffer feature of the output compare unit is enabled in the fast pwm mode. tcntn ocrnx update and tovn interrupt flag set 1 period 2 3 ocn ocn (comnx1:0 = 2) (comnx1:0 = 3) ocrnx interrupt flag set 4 5 6 7 f ocnxpwm f clk_i/o n 256 ? -------------------- - = 169 4921e?auto?09/09 ata6602/ata6603 4.15.6.4 phase correct pwm mode the phase correct pwm mode (wgm22:0 = 1 or 5) provides a high resolution phase correct pwm waveform generation option. the phase correct pwm mode is based on a dual-slope operation. the counter counts repeatedly from bottom to top and then from top to bot- tom. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7. in non-inverting compare output mode, the output compare (oc2x) is cleared on the compare match between tcnt2 and ocr2x while upcounting, and set on the compare match while downcounting. in inverting output compare mode, the operation is inverted. the dual-slope operation has lower maximum operation frequency than single slope operation. however, due to the symmetric feature of the dual-slope pwm modes, these modes are preferred for motor con- trol applications. in phase correct pwm mode the counter is incremented until the counter value matches top. when the counter reaches top, it changes the count direction. the tcnt2 value will be equal to top for one timer clock cycle. the timing diagram for the phase correct pwm mode is shown on figure 4-59 . the tcnt2 value is in the timing diagram shown as a histogram for illustrating the dual-slope operation. the diagram includes non-inverted and inverted pwm outputs. the small horizontal line marks on the tcnt2 sl opes represent compare matches between ocr2x and tcnt2. figure 4-59. phase correct pwm mode, timing diagram the timer/counter overflow flag (tov2) is set each time the counter reaches bottom. the interrupt flag can be used to generate an interrupt each time the counter reaches the bottom value. tovn interrupt flag set ocnx interrupt flag set 1 2 3 tcntn period ocn ocn (comnx1:0 = 2) (comnx1:0 = 3) ocrnx update 170 4921e?auto?09/09 ata6602/ata6603 in phase correct pwm mode, the compare unit allows generation of pwm waveforms on the oc2x pin. setting the com2x1:0 bits to two w ill produce a non-inverted pwm. an inverted pwm output can be generated by setting the com2x1:0 to three. top is defined as 0xff when wgm2:0 = 3, and ocr2a when mgm2:0 = 7 (see table 4-60 on page 173 ). the actual oc2x value will only be visible on the port pin if the data direction for the port pin is set as output. the pwm waveform is generated by clearing (or setting) the oc2x register at the compare match between ocr2x and tcnt2 when the counter increments, and setting (or clearing) the oc2x register at compare match between ocr2x and tcnt2 when the counter decrements. the pwm frequency for the output when using phase correct pwm can be calculated by the follow- ing equation: the n variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024). the extreme values for the ocr2a register represent special cases when generating a pwm waveform output in the phase correct pwm mode. if the ocr2a is set equal to bottom, the output will be continuously low an d if set equal to max the output will be continuously high for non-inverted pwm mode. for in verted pwm the output will have the opposite logic values. at the very start of period 2 in figure 4-59 on page 169 ocnx has a transition from high to low even though there is no compare match. the poin t of this transition is to guarantee symmetry around bottom. there are two cases that give a transition without compare match. ? ocr2a changes its value from max, like in figure 4-59 on page 169 . when the ocr2a value is max the ocn pin value is the same as the result of a down-counting compare match. to ensure symmetry around bottom the ocn value at max must correspond to the result of an up-counting compare match. ? the timer starts counting from a value higher than the one in ocr2a, and for that reason misses the compare match and hence the ocn change that would have happened on the way up. 4.15.7 timer/counter timing diagrams the following figures show the timer/counter in synchronous mode, and the timer clock (clk t2 ) is therefore shown as a clock enable signal. in asynchronous mode, clk i/o should be replaced by the timer/counter oscillator clock. the figures include information on when interrupt flags are set. figure 4-60 contains timing data for basic timer/ counter operation. the figure shows the count sequence close to the max value in all modes other than phase correct pwm mode. figure 4-60. timer/counter timing diagram, no prescaling f ocnxpcpwm f clk_i/o n 510 ? -------------------- - = clk tn (clk i/o /1) tovn clk i/o tcntn max - 1 max bottom bottom + 1 171 4921e?auto?09/09 ata6602/ata6603 figure 4-61 shows the same timing data, but with the prescaler enabled. figure 4-61. timer/counter timing dia gram, with prescaler (f clk_i/o /8) figure 4-62 shows the setting of ocf2a in all modes except ctc mode. figure 4-62. timer/counter timing diagram, setting of ocf2a, with prescaler (f clk_i/o /8) figure 4-63 shows the setting of ocf2a and the clearing of tcnt2 in ctc mode. figure 4-63. timer/counter timing diagram, clear timer on compare match mode, with pres- caler (f clk_i/o /8) tovn tcntn max - 1 max bottom bottom + 1 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn ocrnx value ocrnx - 1 ocrnx ocrnx + 1 ocrnx + 2 clk i/o clk tn (clk i/o /8) ocfnx ocrnx tcntn (ctc) top top - 1 top bottom bottom + 1 clk i/o clktn (clk i/o /8) 172 4921e?auto?09/09 ata6602/ata6603 4.15.8 8-bit timer/counte r register description 4.15.8.1 timer/coun ter control regi ster a ? tccr2a ? bits 7:6 ? com2a1:0: compare match output a mode these bits control the output compare pin (oc2a) behavior. if one or both of the com2a1:0 bits are set, the oc2a output overri des the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit correspond- ing to the oc2a pin must be set in order to enable the output driver. when oc2a is connected to the pin, the function of the com2a1:0 bits depends on the wgm22:0 bit setting. table 4-58 shows the com2a1:0 bit functionality when the wgm22:0 bits are set to a normal or ctc mode (non-pwm). table 4-59 shows the com2a1:0 bit functionality when the wgm21:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?fast pwm mode? on page 167 for more details. bit 7 6 5 4 3 210 com2a1 com2a0 com2b1 com2b0 ? ? wgm21 wgm20 tccr2a read/write r/w r/w r/w r/w r r r/w r/w initial value 0 0 0 0 0 0 0 0 table 4-58. compare output mode, non-pwm mode com2a1 com2a0 description 0 0 normal port operation, oc0a disconnected. 0 1 toggle oc2a on compare match 1 0 clear oc2a on compare match 1 1 set oc2a on compare match table 4-59. compare output mode, fast pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01 wgm22 = 0: normal port oper ation, oc0a disconnected. wgm22 = 1: toggle oc2a on compare match. 1 0 clear oc2a on compare match, set oc2a at top 1 1 set oc2a on compare match, clear oc2a at top 173 4921e?auto?09/09 ata6602/ata6603 table 4-60 shows the com2a1:0 bit functionality when the wgm22:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs when ocr2a equals top and com2a1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 169 for more details. ? bits 5:4 ? com2b1:0: compare match output b mode these bits control the output compare pin (oc2b) behavior. if one or both of the com2b1:0 bits are set, the oc2b output overri des the normal port functionality of the i/o pin it is connected to. however, note that the data direction register (ddr) bit correspond- ing to the oc2b pin must be set in order to enable the output driver. when oc2b is connected to the pin, the function of the com2b1:0 bits depends on the wgm22:0 bit setting. table 4-61 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to a normal or ctc mode (non-pwm). table 4-62 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to fast pwm mode. note: 1. a special case occurs when ocr2b equals top and com2b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 169 for more details. table 4-60. compare output mode, phase correct pwm mode (1) com2a1 com2a0 description 0 0 normal port operation, oc2a disconnected. 01 wgm22 = 0: normal port operation, oc2a disconnected. wgm22 = 1: toggle oc2a on compare match. 10 clear oc2a on compare match when up-counting. set oc2a on compare match when down-counting. 11 set oc2a on compare match when up-counting. clear oc2a on compare match when down-counting. table 4-61. compare output mode, non-pwm mode com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 0 1 toggle oc2b on compare match 1 0 clear oc2b on compare match 1 1 set oc2b on compare match table 4-62. compare output mode, fast pwm mode (1) com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 01reserved 1 0 clear oc2b on compare match, set oc2b at top 1 1 set oc2b on compare match, clear oc2b at top 174 4921e?auto?09/09 ata6602/ata6603 table 4-63 shows the com2b1:0 bit functionality when the wgm22:0 bits are set to phase cor- rect pwm mode. note: 1. a special case occurs when ocr2b equals top and com2b1 is set. in this case, the com- pare match is ignored, but the set or clear is done at top. see ?phase correct pwm mode? on page 169 for more details. ? bits 3, 2 ? res: reserved bits these bits are reserved bits in the ata 6602/ata6603 and will always read as zero. ? bits 1:0 ? wgm21:0: waveform generation mode combined with the wgm22 bit found in the tccr2b register, these bits control the counting sequence of the counter, the source for maximum (top) counter value, and what type of wave- form generation to be used, see table 4-64 . modes of operation supported by the timer/counter unit are: normal mode (counter), clear timer on compare match (ctc) mode, and two types of pulse width modulation (pwm) modes (see ?modes of operation? on page 166 ). notes: 1. max= 0xff 2. bottom= 0x00 table 4-63. compare output mode, phase correct pwm mode (1) com2b1 com2b0 description 0 0 normal port operation, oc2b disconnected. 01reserved 10 clear oc2b on compare match when up-counting. set oc2b on compare match when down-counting. 11 set oc2b on compare match when up-counting. clear oc2b on compare match when down-counting. table 4-64. waveform generation mode bit description mode wgm2 wgm1 wgm0 timer/counter mode of operation top update of ocrx at tov flag set on (1)(2) 0 0 0 0 normal 0xff immediate max 10 0 1 pwm, phase correct 0xff top bottom 2 0 1 0 ctc ocra immediate max 3 0 1 1 fast pwm 0xff top max 4 1 0 0 reserved ? ? ? 51 0 1 pwm, phase correct ocra top bottom 6 1 1 0 reserved ? ? ? 7 1 1 1 fast pwm ocra top top 175 4921e?auto?09/09 ata6602/ata6603 4.15.8.2 timer/coun ter control regi ster b ? tccr2b ? bit 7 ? foc2a: force output compare a the foc2a bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr2b is written when operating in pwm mode . when writing a logi cal one to the foc2a bit, an immediate compare match is forced on the waveform generation unit. the oc2a output is changed according to its com2a1:0 bits setting. note that the foc2a bit is imple- mented as a strobe. therefore it is the value present in the com2a1:0 bits that determines the effect of the forced compare. a foc2a strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2a as top. the foc2a bit is always read as zero. ? bit 6 ? foc2b: force output compare b the foc2b bit is only active when the wgm bits specify a non-pwm mode. however, for ensuring compatibility with future devices, this bit must be set to zero when tccr2b is written when operating in pwm mode . when writing a logi cal one to the foc2b bit, an immediate compare match is forced on the waveform generation unit. the oc2b output is changed according to its com2b1:0 bits setting. note that the foc2b bit is imple- mented as a strobe. therefore it is the value present in the com2b1:0 bits that determines the effect of the forced compare. a foc2b strobe will not generate any interrupt, nor will it clear the timer in ctc mode using ocr2b as top. the foc2b bit is always read as zero. ? bits 5:4 ? res: reserved bits these bits are reserved bits in the ata 6602/ata6603 and will always read as zero. ? bit 3 ? wgm22: waveform generation mode see the description in ?timer/counter control register a ? tccr2a? on page 172 . ? bit 2:0 ? cs22:0: clock select the three clock select bits select the clock source to be used by the timer/counter (see table 4-65 on page 176 ). bit 7 6 5 4 3 210 foc2afoc2b ? ? wgm22cs22cs21cs20tccr2b read/write w w r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 176 4921e?auto?09/09 ata6602/ata6603 if external pin modes are used for the timer/counter0, transitions on the t0 pin will clock the counter even if the pin is configured as an output. this feature allows software control of the counting. 4.15.8.3 timer/counter register ? tcnt2 the timer/counter register gives direct ac cess, both for read and write operations, to the timer/counter unit 8-bit counter. writing to the tcnt2 register blocks (removes) the compare match on the following timer clock. modifying the counter (tcnt2) while the counter is running, introduces a risk of missing a compare match between tcnt2 and the ocr2x registers. 4.15.8.4 output compare register a ? ocr2a the output compare register a contains an 8-bi t value that is continuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2a pin. 4.15.8.5 output compare register b ? ocr2b the output compare register b contains an 8-bi t value that is continuously compared with the counter value (tcnt2). a match can be used to generate an output compare interrupt, or to generate a waveform output on the oc2b pin. table 4-65. clock select bit description cs22 cs21 cs20 description 0 0 0 no clock source (timer/counter stopped). 001clk t2s /(no prescaling) 010clk t2s /8 (from prescaler) 011clk t2s /32 (from prescaler) 100clk t2s /64 (from prescaler) 101clk t2s /128 (from prescaler) 110clk t 2 s /256 (from prescaler) 111clk t 2 s /1024 (from prescaler) bit 76543210 tcnt2[7:0] tcnt2 read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr2a[7:0] ocr2a read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 ocr2b[7:0] ocr2b read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 177 4921e?auto?09/09 ata6602/ata6603 4.15.8.6 timer/counter2 interrupt mask register ? timsk2 ? bit 2 ? ocie2b: timer/counter2 output compare match b interrupt enable when the ocie2b bit is written to one and the i-bit in the status register is set (one), the timer/counter2 compare match b interrupt is enabled. the corresponding interrupt is exe- cuted if a compare match in timer/counter2 occurs, i.e., when the ocf2b bit is set in the timer/counter 2 interrupt flag register ? tifr2. ? bit 1 ? ocie2a: timer/counter2 output compare match a interrupt enable when the ocie2a bit is written to one and the i-bit in the status register is set (one), the timer/counter2 compare match a interrupt is enabled. the corresponding interrupt is exe- cuted if a compare match in timer/counter2 occurs, i.e., when the ocf2a bit is set in the timer/counter 2 interrupt flag register ? tifr2. ? bit 0 ? toie2: timer/counter2 overflow interrupt enable when the toie2 bit is written to one and the i-bit in the status register is set (one), the timer/counter2 overflow interrupt is enabled. the corresponding interrupt is executed if an overflow in timer/counter2 occurs, i.e., when the tov2 bit is set in the timer/counter2 interrupt flag register ? tifr2. 4.15.8.7 timer/counter2 interrupt flag register ? tifr2 ? bit 2 ? ocf2b: output compare flag 2 b the ocf2b bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2b ? output compare register2. ocf2b is cleared by hardware when exe- cuting the corresponding interrupt handling vector. alternatively, ocf2b is cleared by writing a logic one to the flag. when the i- bit in sreg, ocie2b (timer/counter2 compare match interrupt enable), and ocf2b are set (one), the timer/counter2 compare match interrupt is executed. ? bit 1 ? ocf2a: output compare flag 2 a the ocf2a bit is set (one) when a compare match occurs between the timer/counter2 and the data in ocr2a ? output compare register2. ocf2a is cleared by hardware when exe- cuting the corresponding interrupt handling vector. alternatively, ocf2a is cleared by writing a logic one to the flag. when the i- bit in sreg, ocie2a (timer/counter2 compare match interrupt enable), and ocf2a are set (one), the timer/counter2 compare match interrupt is executed. bit 76543 2 1 0 ? ? ? ? ? ocie2b ocie2a toie2 timsk2 read/write r rrrr r/wr/wr/w initial value 0 0 0 0 0 0 0 0 bit 76543210 ?????ocf2bocf2atov2tifr2 read/writerrrrrr/wr/wr/w initial value00000000 178 4921e?auto?09/09 ata6602/ata6603 ? bit 0 ? tov2: timer/counter2 overflow flag the tov2 bit is set (one) when an overflow occurs in timer/counter2. tov2 is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, tov2 is cleared by writing a logic one to the flag. when the sreg i-bit, toie2a (timer/counter2 overflow interrupt enable), and tov2 are set (one), the timer/counter2 overflow interrupt is executed. in pwm mode, this bit is set when timer/counter2 changes counting direction at 0x00. 4.15.9 asynchronous operation of the timer/counter 4.15.9.1 asynchronous operation of timer/counter2 when timer/counter2 operates asynchronously, some considerations must be taken. ? warning: when switching between asynchronous and synchronous clocking of timer/counter2, the timer registers tcnt2, ocr2x, and tccr2x might be corrupted. a safe procedure for switching clock source is: a. disable the timer/counter2 interrupts by clearing ocie2x and toie2. b. select clock source by setting as2 as appropriate. c. write new values to tcnt2, ocr2x, and tccr2x. d. to switch to asynchronous operation: wait for tcn2xub, ocr2xub, and tcr2xub. e. clear the timer/counter2 interrupt flags. f. enable interrupts, if needed. ? the cpu main clock frequency must be more than four times th e oscillator frequency. ? when writing to one of the registers tcnt2, ocr2x, or tccr2x, the value is transferred to a temporary register, and latched after two positive edges on tosc1. the user should not write a new value before the contents of the temporary register have been transferred to its destination. each of the five mentioned registers have their individual temporary register, which means that e.g. writing to tcnt2 does not disturb an ocr2x write in progress. to detect that a transfer to the destination register has taken place, the asynchronous status register ? assr has been implemented. ? when entering power-save or adc noise reduction mode after having written to tcnt2, ocr2x, or tccr2x, the user must wait until the written register has been updated if timer/counter2 is used to wake up the device. otherwise, the mcu will enter sleep mode before the changes are effective. this is particularly important if any of the output compare2 interrupt is used to wake up the device, sinc e the output compare function is disabled during writing to ocr2x or tcnt2. if the write cycle is not finished, and the mcu enters sleep mode before the corresponding ocr2 xub bit returns to zero, the device will never receive a compare match interrupt, and the mcu will not wake up. ? if timer/counter2 is used to wake the device up from power-save or adc noise reduction mode, precautions must be taken if the user wants to re-enter one of these modes: the interrupt logic needs one tosc1 cycle to be reset. if the time between wake-up and re-entering sleep m ode is less than one tosc1 cycle, the interrupt will not occur, and the device will fail to wake up. if the user is in doubt whether the ti me before re-entering power-save or adc noise reduction mode is sufficient, the following algorithm can be used to ensure that one tosc1 cycle has elapsed: 179 4921e?auto?09/09 ata6602/ata6603 a. write a value to tccr2x, tcnt2, or ocr2x. b. wait until the corresponding update busy flag in assr returns to zero. c. enter power-save or adc noise reduction mode. ? when the asynchronous operatio n is selected, the 32.768 khz oscillator for timer/counter2 is always running, except in power-down and standby modes. after a power-up reset or wake-up from power-down or standby mode, the user should be aware of the fact that this oscillator might take as long as one second to stabilize. the user is advised to wait for at least one second before using timer/counter2 after power-up or wake-up from power-down or standby mode. the contents of all timer/coun ter2 registers must be considered lost after a wake-up from power-down or standby mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use or a clock signal is applied to the tosc1 pin. ? description of wake up from power-save or adc noise reduction mode when the timer is clocked asynchronously: when the interrupt condition is met, the wake up process is started on the following cycle of the timer clock, that is, the timer is always advanced by at least one before the processor can read the counter value. after wake-up, the mcu is halted for four cycles, it executes the interrupt routine, and resumes execution from the instruction following sleep. ? reading of the tcnt2 register shortly after wake-up from power-save may give an incorrect result. since tcnt2 is clocked on the asynchronous tosc clock, reading tcnt2 must be done through a register synchronized to the internal i/o clock domain. synchronization takes place for every rising tosc1 edge. when waking up from power-save mode, and the i/o clock (clk i/o ) again becomes active, tcnt2 will read as the previous value (before entering sleep) until the next rising tosc1 edge. the phase of the tosc clock after waking up from power-save mode is essentially unpredictable, as it depends on the wake-up time. the recommended procedure for reading tcnt2 is thus as follows: a. write any value to either of the registers ocr2x or tccr2x. b. wait for the corresponding update busy flag to be cleared. c. read tcnt2. during asynchronous operation, the synchronizati on of the interrupt flags for the asynchronous timer takes 3 processor cycles plus one timer cycle. the timer is therefore advanced by at least one before the processor can read the timer value causing the setting of the interrupt flag. the output compare pin is changed on the timer clock and is not synchronized to the processor clock. 4.15.9.2 asynchronous status register ? assr ? bit 6 ? exclk: enable external clock input when exclk is written to one, and asynchronous clock is selected, the external clock input buffer is enabled and an external clock can be input on timer oscillator 1 (tosc1) pin instead of a 32 khz crystal. writing to exclk should be done before asynchronous opera- tion is selected. note that the crystal osc illator will only run when this bit is zero. bit 7 6 5 4 3 2 1 0 ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub assr read/write r r/w r/w r r r r r initial value 0 0 0 0 0 0 0 0 180 4921e?auto?09/09 ata6602/ata6603 ? bit 5 ? as2: asynchronous timer/counter2 when as2 is written to zero, timer/counter2 is clocked from the i/o clock, clki/o. when as2 is written to one, timer/counter2 is clocked from a crystal oscillator connected to the timer oscillator 1 (tosc1) pin. when the val ue of as2 is changed, the contents of tcnt2, ocr2a, ocr2b, tccr2a and tccr2b might be corrupted. ? bit 4 ? tcn2ub: time r/counter2 update busy when timer/counter2 operates asynchronously and tcnt2 is written, this bit becomes set. when tcnt2 has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tcnt2 is ready to be updated with a new value. ? bit 3 ? ocr2aub: output compare register2 update busy when timer/counter2 operates asynchronously and ocr2a is written, this bit becomes set. when ocr2a has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that ocr2a is ready to be updated with a new value. ? bit 2 ? ocr2bub: output compare register2 update busy when timer/counter2 operates asynchronously and ocr2b is written, this bit becomes set. when ocr2b has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that ocr2b is ready to be updated with a new value. ? bit 1 ? tcr2aub: timer/counter control register2 update busy when timer/counter2 operates asynchronously and tccr2a is written, this bit becomes set. when tccr2a has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2a is ready to be updated with a new value. ? bit 0 ? tcr2bub: timer/counte r control register2 update busy when timer/counter2 operates asynchronously and tccr2b is written, this bit becomes set. when tccr2b has been updated from the temporary storage register, this bit is cleared by hardware. a logical zero in this bit indicates that tccr2b is ready to be updated with a new value. if a write is performed to any of the five timer/counter2 registers while its update busy flag is set, the updated value might get corrupted and cause an unintentional interrupt to occur. the mechanisms for reading tcnt2, ocr2a, ocr2b, tccr2a and tccr2b are differ- ent. when reading tcnt2, the actual timer value is read. when reading ocr2a, ocr2b, tccr2a and tccr2b the value in the te mporary storage re gister is read. 181 4921e?auto?09/09 ata6602/ata6603 4.15.10 timer/counter prescaler figure 4-64. prescaler for timer/counter2 the clock source for timer/counter2 is named clk t2s . clk t2s is by default connected to the main system i/o clock clk i o . by setting the as2 bit in assr, timer/counter2 is asynchronously clocked from the tosc1 pin. this enables us e of timer/counter2 as a real time counter (rtc). when as2 is set, pins tosc1 and tosc 2 are disconnected from port c. a crystal can then be connected between the tosc1 and tosc2 pins to serve as an independent clock source for timer/counter2. the oscillator is optimized for use with a 32.768 khz crystal. apply- ing an external clock source to tosc1 is not recommended. for timer/counter2, the possible prescaled selections are: clk t2s /8, clk t2s /32, clk t2s /64, clk t2s /128, clk t2s /256, and clk t2s /1024. additionally, clk t2s as well as 0 (stop) may be selected. setting the psrasy bit in gtccr resets the prescale r. this allows the user to operate with a predictable prescaler. 4.15.10.1 general timer/counter control register ? gtccr ? bit 1 ? psrasy: prescaler reset timer/counter2 when this bit is one, the timer/counter2 prescaler will be reset. this bit is normally cleared immediately by hardware. if the bit is written when timer/counter2 is operating in asynchro- nous mode, the bit will remain one until the prescaler has been reset. the bit will not be cleared by hardware if the tsm bit is set. refer to the description of the ?bit 7 ? tsm: timer/counter synchronization mode? on page 131 for a description of the timer/counter synchronization mode. 10-bit t/c prescaler timer/counter2 clock source clk i/o clk t2s tosc1 as2 cs20 cs21 cs22 clk t2s /8 clk t2s /64 clk t2s /128 clk t2s /1024 clk t2s /256 clk t2s /32 0 psrasy clear clk t2 bit 7 6 5 4 3 2 1 0 tsm ? ? ? ? ?psrasy psrsync gtccr read/write r/w r r r r r r/w r/w initial value 0 0 0 0 0 0 0 0 182 4921e?auto?09/09 ata6602/ata6603 4.16 serial peripheral interface ? spi the serial peripheral interface (spi) allows hi gh-speed synchronous data transfer between the ata6602/ata6603 and peripheral devices or between several avr devices. the ata6602/ata6603 spi includes the following features: ? full-duplex, three-wire synchronous data transfer ? master or slave operation ? lsb first or msb first data transfer ? seven programmable bit rates ? end of transmission interrupt flag ? write collision flag protection ? wake-up from idle mode ? double speed (ck/2) master spi mode the usart can also be used in master spi mode (see ?usart in spi mode? on page 218 ). the prspi bit in ?power reduction register - prr? on page 64 must be written to zero to enable spi module. figure 4-65. spi block diagram (1) note: 1. refer to table 4-32 on page 95 for spi pin placement. spi2x spi2x divider /2/4/8/16/32/64/128 internal data b u s spi interrupt request 8 8 8 spi control register spi status register spi control select xtal spi clock (master) mstr spe msb lsb 8 bit shift register read data buffer clock clock logic s m ss sck mosi miso s m m s spr0 spr1 cpha cpol mstr dord spe spie wcol spif spr1 spr0 pin control logic mstr spe dord 183 4921e?auto?09/09 ata6602/ata6603 the interconnection between master and slave cpus with spi is shown in figure 4-66 . the sys- tem consists of two shift registers, and a master clock generator. the spi master initiates the communication cycle when pu lling low the slave select ss pin of the desired slave. master and slave prepare the data to be sent in their respective shift registers, and the master generates the required clock pulses on the sck line to interchange data. data is always shifted from mas- ter to slave on the master out ? slave in, mosi, line, and from slave to master on the master in ? slave out, miso, line. after ea ch data packet, the master will synchronize the slave by pulling high the slave select, ss , line. when configured as a master, the spi interface has no automatic control of the ss line. this must be handled by user software before communication can start. when this is done, writing a byte to the spi data register starts the spi clock generator, and the hardware shifts the eight bits into the slave. after shifting one byte , the spi clock generator stops, setting the end of transmission flag (spif). if the spi interrupt enable bit (spie) in the spcr register is set, an interrupt is requested. the master may continue to shift the next byte by writing it into spdr, or signal the end of packet by pulling high the slave select, ss line. the last incoming byte will be kept in the buffer register for later use. when configured as a slave, the spi interface will remain sleeping with miso tri-stated as long as the ss pin is driven high. in this state, software may update the contents of the spi data register, spdr, but the data will not be shifted out by incoming clock pulses on the sck pin until the ss pin is driven low. as one byte has been completely shifted, the end of transmission flag, spif is set. if the spi interrupt enable bit, spie, in the spcr register is set, an interrupt is requested. the slave may continue to place new data to be sent into spdr before reading the incoming data. the last incoming byte will be kept in the buffer register for later use. figure 4-66. spi master-slave interconnection the system is single buffered in the transmit di rection and double buffered in the receive direc- tion. this means that bytes to be transmitted cannot be written to the spi data register before the entire shift cycle is complet ed. when receiving data, however, a received character must be read from the spi data register before the next character has been completely shifted in. oth- erwise, the first byte is lost. shift enable sck sck ss ss mosi mosi miso miso msb master lsb 8 bit shift register 8 bit shift register msb slave lsb spi clock generator 184 4921e?auto?09/09 ata6602/ata6603 in spi slave mode, the control logic will sample the incoming signal of the sck pin. to ensure correct sampling of the clock signal, the frequency of the spi clock should never exceed f osc /4. when the spi is enabled, the data direction of the mosi, miso, sck, and ss pins is overridden according to table 4-66 . for more details on automatic port overrides, refer to ?alternate port functions? on page 93 . note: 1. see ?alternate functions of port b? on page 95 for a detailed description of how to define the direction of the user defined spi pins. the following code examples show how to initialize the spi as a master and how to perform a simple transmission. ddr_spi in the examples mu st be replaced by the actual data direction register controlling the spi pins. dd_mosi, dd_miso and dd_sck must be replaced by the actual data direction bits for these pins. e.g. if mosi is placed on pin pb5, replace dd_mosi with ddb5 and ddr_spi with ddrb. table 4-66. spi pin overrides (1) pin direction, master spi direction, slave spi mosi user defined input miso input user defined sck user defined input ss user defined input 185 4921e?auto?09/09 ata6602/ata6603 note: 1. the example code assumes that the pa rt specific header file is included. assembly code example (1) spi_masterinit: ; set mosi and sck output, all others input ldi r17,(1< 188 4921e?auto?09/09 ata6602/ata6603 ? bit 4 ? mstr: master/slave select this bit selects master spi mode when written to one, and slave spi mode when written logic zero. if ss is configured as an input and is driven low while mstr is set, mstr will be cleared, and spif in spsr will become set. the user will then have to set mstr to re-enable spi master mode. ? bit 3 ? cpol: clock polarity when this bit is written to one, sck is high wh en idle. when cpol is written to zero, sck is low when idle . refer to figure 4-67 and figure 4-68 for an example. the cpol functionality is summarized below: ? bit 2 ? cpha: clock phase the settings of the clock phase bit (cpha) determine if data is sampled on the leading (first) or trailing (last) edge of sck. refer to figure 4-67 and figure 4-68 for an example. the cpol functionality is summarized below: ? bits 1, 0 ? spr1, spr0: spi clock rate select 1 and 0 these two bits control the sck rate of the device configured as a master. spr1 and spr0 have no effect on the slave. the relationship between sck and the oscillator clock fre- quency f osc is shown in the following table: table 4-67. cpol functionality cpol leading edge trailing edge 0 rising falling 1 falling rising table 4-68. cpha functionality cpha leading edge trailing edge 0 sample setup 1 setup sample table 4-69. relationship between sck and the oscillator frequency spi2x spr1 spr0 sck frequency 000 f osc / 4 001 f osc / 16 010 f osc / 64 011 f osc / 128 100 f osc / 2 101 f osc / 8 110 f osc / 32 111 f osc / 64 189 4921e?auto?09/09 ata6602/ata6603 4.16.1.4 spi status register ? spsr ? bit 7 ? spif: spi interrupt flag when a serial transfer is complete, the spif flag is set. an interrupt is generated if spie in spcr is set and global interrupts are enabled. if ss is an input and is driven low when the spi is in master mode, this will also set t he spif flag. spif is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, the spif bit is cleared by first reading the spi status register with spif set, then accessing the spi data register (spdr). ? bit 6 ? wcol: write collision flag the wcol bit is set if the spi data register (spdr) is written during a data transfer. the wcol bit (and the spif bit) are cleared by first reading the spi status register with wcol set, and then accessing the spi data register. ? bit 5..1 ? res: reserved bits these bits are reserved bits in the ata 6602/ata6603 and will always read as zero. ? bit 0 ? spi2x: double spi speed bit when this bit is written logi c one the spi speed (sck frequency) will be doubled when the spi is in master mode (see table 4-69 on page 188 ). this means that the minimum sck period will be two cpu clock periods. when the sp i is configured as sl ave, the spi is only guaranteed to work at fosc/4 or lower. the spi interface on the ata6602/ata6603 is also used for program memory and eeprom downloading or uploading. see ?serial downloading? on page 313 for serial pro- gramming and verification. 4.16.1.5 spi data register ? spdr the spi data register is a read/write register used for data transfer between the register file and the spi shift register. writing to the register initiates data transmission. reading the regis- ter causes the shift register receive buffer to be read. bit 76543210 spifwcol?????spi2x spsr read/writerrrrrrrr/w initial value00000000 bit 76543210 msb lsb spdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value x x x x x x x x undefined 190 4921e?auto?09/09 ata6602/ata6603 4.16.2 data modes there are four combinations of sck phase and polarity with respect to serial data, which are determined by control bits cpha and cpol. the spi data transfer formats are shown in figure 4-67 and figure 4-68 . data bits are shifted out and latched in on opposite edges of the sck sig- nal, ensuring sufficient time for data signals to st abilize. this is clearly seen by summarizing table 4-67 and table 4-68 , as done below. figure 4-67. spi transfer format with cpha = 0 figure 4-68. spi transfer format with cpha = 1 table 4-70. cpol functionality leading edge trailing edge spi mode cpol=0, cpha=0 sample (rising) setup (falling) 0 cpol=0, cpha=1 setup (rising) sample (falling) 1 cpol=1, cpha=0 sample (falling) setup (rising) 2 cpol=1, cpha=1 setup (falling) sample (rising) 3 bit 1 bit 6 lsb msb sck (cpol = 0) mode 0 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 2 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 msb first (dord = 0) lsb first ( dord = 1 ) sck (cpol = 0) mode 1 sample i mosi/miso change 0 mosi pin change 0 miso pin sck (cpol = 1) mode 3 ss msb lsb bit 6 bit 1 bit 5 bit 2 bit 4 bit 3 bit 3 bit 4 bit 2 bit 5 bit 1 bit 6 lsb msb msb first (dord = 0) lsb first ( dord = 1 ) 191 4921e?auto?09/09 ata6602/ata6603 4.17 usart0 the universal synchronous and asynchronous serial receiver and transmitter (usart) is a highly flexible serial communication device. the main features are: ? full duplex operation (independent se rial receive and transmit registers) ? asynchronous or synchronous operation ? master or slave clocked synchronous operation ? high resolution baud rate generator ? supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits ? odd or even parity generation and parity check supported by hardware ? data overrun detection ? framing error detection ? noise filtering includes false start bit detection and digital low pass filter ? three separate interrupts on tx complete, tx data register empty and rx complete ? multi-processor communication mode ? double speed asynchronous communication mode the usart can also be used in master spi mode (see ?usart in spi mode? on page 218 . the power reduction usart bit, prusart0, in ?power reduction register - prr? on page 64 must be disabled by writing a logical zero to it. 4.17.1 overview a simplified block diagram of the usart transmitter is shown in figure 4-69 on page 192 . cpu accessible i/o registers and i/o pins are shown in bold. 192 4921e?auto?09/09 ata6602/ata6603 figure 4-69. usart block diagram (1) note: 1. refer to table 4-38 on page 102 for usart0 pin placement. the dashed boxes in the block diagram separate the three main parts of the usart (listed from the top): clock generator, transmitter and receiver. control registers are shared by all units. the clock generation logic consis ts of synchronization logic fo r external clock input used by synchronous slave operation, and the baud rate generator. the xckn (transfer clock) pin is only used by synchronous transfer mode. the transmi tter consists of a single write buffer, a serial shift register, parity generator and cont rol logic for handling different serial frame for- mats. the write buffer allows a continuous transfer of data without any delay between frames. the receiver is the most complex part of the usart module due to its clock and data recovery units. the recovery units are used for asynchronous data reception. in addition to the recovery units, the receiver includes a parity checker, control logic, a shift register and a two level receive buffer (udrn). the receiver supports the same frame formats as the transmitter, and can detect frame error, data overrun and parity errors. parity generator ubrrn [h:l] udrn(transmit) ucsrna ucsrnb ucsrnc baud rate generator transmit shift register receive shift register rxdn txdn pin control udrn(receive) pin control xckn data recovery clock recovery pin control tx control rx control parity checker data bus osc sync logic clock generator transmitter receiver 193 4921e?auto?09/09 ata6602/ata6603 4.17.2 clock generation the clock generation logic generates the base clock for the transmitter and receiver. the usart supports four modes of clock operati on: normal asynchronous, double speed asyn- chronous, master synchronous and slave synchronous mode. the umseln bit in usart control and status register c (ucsrnc) selects between asynchronous and synchronous operation. double speed (asynchronous mode only) is controlled by the u2xn found in the ucsrna register. when using synchronous mode (umseln = 1), the data direction register for the xckn pin (ddr_xckn) controls whether the clock source is internal (master mode) or external (slave mode). the xckn pin is only active when using synchronous mode. figure 4-70 shows a block diagram of the clock generation logic. figure 4-70. clock generation logic, block diagram signal description: txclk transmitter clock (internal signal). rxclk receiver base clock (internal signal). xcki input from xck pin (internal signal). used for synchronous slave operation. xcko clock output to xck pin (internal signal). used for synchronous master operation. fosc xtal pin frequency (system clock). 4.17.2.1 internal clock generation ? the baud rate generator internal clock generation is used for the as ynchronous and the synchronous master modes of operation. the description in this section refers to figure 4-70 . the usart baud rate register (ubrrn) and the down-counter connected to it function as a programmable prescaler or baud rate generator. the down-counter, running at system clock (f osc ), is loaded with the ubrrn value each time the counter has counted down to zero or when the ubrrnl register is written. a clock is gene rated each time the counter reaches zero. this clock is the baud rate generator clock output (= f osc /(ubrrn+1)). the transmitter divides the baud rate generator clock output by 2, 8 or 16 depending on mode. the baud rate generator out- put is used directly by the receiver?s clock an d data recovery units. however, the recovery units use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the umseln, u2xn and ddr_xckn bits. prescaling down-counter /2 ubrrn /4 /2 foscn ubrrn+1 sync register osc xckn pin txclk u2xn umseln ddr_xckn 0 1 0 1 xcki xcko ddr_xckn rxclk 0 1 1 0 edge detector ucpoln 194 4921e?auto?09/09 ata6602/ata6603 table 4-71 contains equations for calculating the baud rate (in bits per second) and for calculat- ing the ubrrn value for each mode of operation using an internally generated clock source. note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095) some examples of ubrrn values for some system clock frequencies are found in table 4-79 on page 216 (see ?examples of ubrrn settings for commonly used oscillator frequencies? on page 216 ). 4.17.2.2 double speed operation (u2xn) the transfer rate can be doubled by setting the u2xn bit in ucsrna. setting this bit only has effect for the asynchronous operation. set this bit to zero when using synchronous operation. setting this bit will reduce the divisor of the baud rate divider from 16 to 8, effectively doubling the transfer rate for asynchronous communication. note however that the receiver will in this case only use half the number of samples (reduced from 16 to 8) for data sampling and clock recovery, and therefore a more accurate baud rate setting and system clock are required when this mode is used. for the transmitter, there are no downsides. table 4-71. equations for calculating baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrrn value asynchronous normal mode (u2xn = 0) asynchronous double speed mode (u2xn = 1) synchronous master mode baud f osc 16 ubrr n 1 + () ----------------------------------------- - = ubrr n f osc 16 baud ----------------------- - 1 ? = baud f osc 8 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 8 baud -------------------- 1 ? = baud f osc 2 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = 195 4921e?auto?09/09 ata6602/ata6603 4.17.2.3 external clock external clocking is used by the synchronous sl ave modes of operation. the description in this section refers to figure 4-70 on page 193 for details. external clock input from the xckn pin is sample d by a synchronization register to minimize the chance of meta-stability. the output from the synchronization register must then pass through an edge detector before it can be used by the transmitter and receiver. this process intro- duces a two cpu clock period delay and therefore the maximum external xckn clock frequency is limited by the following equation: note that f osc depends on the stability of the system clock source. it is therefore recommended to add some margin to avoid possible loss of data due to frequency variations. 4.17.2.4 synchronous clock operation when synchronous mode is used (umseln = 1), th e xckn pin will be used as either clock input (slave) or clock output (master). the dependency between the clock edges and data sampling or data change is the same. the basic principle is that data input (on rxdn) is sampled at the opposite xckn clock edge of the edge the data output (txdn) is changed. figure 4-71. synchronous mode xckn timing the ucpoln bit ucrsc selects which xckn cloc k edge is used for data sampling and which is used for data change. as figure 4-71 shows, when ucpoln is zero the data will be changed at rising xckn edge and sampled at falling xckn edge. if ucpoln is set, the data will be changed at falling xckn edge and samp led at rising xckn edge. f xck f osc 4 ----------- < rxd / txd xck rxd / txd xck ucpol = 0 ucpol = 1 sample sample 196 4921e?auto?09/09 ata6602/ata6603 4.17.3 frame formats a serial frame is defined to be one character of da ta bits with synchronizat ion bits (start and stop bits), and optionally a parity bi t for error checking. the usart accepts all 30 combinations of the following as valid frame formats: ? 1 start bit ? 5, 6, 7, 8, or 9 data bits ? no, even or odd parity bit ? 1 or 2 stop bits a frame starts with the start bit followed by the least significant data bit. then the next data bits, up to a total of nine, are succeeding, ending with t he most significant bit. if enabled, the parity bit is inserted after the data bits, before the stop bits. when a complete frame is transmitted, it can be directly followed by a new frame, or the communication line can be set to an idle (high) state. figure 4-72 illustrates the possible combinations of th e frame formats. bits inside brackets are optional. figure 4-72. frame formats st start bit, always low. (n) data bits (0 to 8). p parity bit. can be odd or even. sp stop bit, always high. idle no transfers on the communication line (rxdn or txdn). an idle line must be high. the frame format used by the usart is set by the ucszn2:0, upmn1:0 and usbsn bits in ucsrnb and ucsrnc. the receiver and transmitter use the same setting. note that changing the setting of any of these bits will corrupt a ll ongoing communication for both the receiver and transmitter. the usart character size (ucszn2:0) bits select the number of data bits in the frame. the usart parity mode (upmn1:0) bits enable and set the type of parity bit. the selection between one or two stop bits is done by the usart st op bit select (usbsn) bi t. the receiver ignores the second stop bit. an fe (f rame error) will theref ore only be detected in the cases where the first stop bit is zero. 1 0 2 3 4 [5] [6] [7] [8] [p] st sp1 [sp2] (st / idle) (idle) frame 197 4921e?auto?09/09 ata6602/ata6603 4.17.3.1 parity bit calculation the parity bit is calculated by do ing an exclusive-or of all the data bits. if odd parity is used, the result of the exclusive or is inverted. the re lation between the parity bit and data bits is as follows: p even parity bit using even parity p odd parity bit using odd parity d n data bit n of the character if used, the parity bit is located between the last data bit and first stop bit of a serial frame. 4.17.4 usart initialization the usart has to be initialized before any communication can take place. the initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the transmitter or the receiver depending on the usage. for interrupt driven usart operation, the global interrupt flag should be cleared (and interrupts globally disabled) when doing the initialization. before doing a re-initialization with changed baud rate or frame format, be sure that there are no ongoing transmissions during the period the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxc flag can be used to check that there are no unread data in the receive buffer. note that the txcn flag must be cleared before each transmission (before udrn is written) if it is used for this purpose. the following simple usart initialization code examples show one assembly and one c func- tion that are equal in functionality. the exampl es assume asynchronous operation using polling (no interrupts enabled) and a fixed frame format. the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. p even d n 1 ? d 3 d 2 d 1 d 0 0 p odd d n 1 ? d 3 d 2 d 1 d 0 1 = = 198 4921e?auto?09/09 ata6602/ata6603 note: 1. the example code assumes that the pa rt specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ? sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. more advanced initialization routines can be made that include frame format as parameters, dis- able interrupts and so on. however, many appl ications use a fixed setting of the baud and control registers, and for these types of applicati ons the initialization code can be placed directly in the main routine, or be combined with initialization code for other i/o modules. assembly code example (1) usart_init: ; set baud rate out ubrrnh, r17 out ubrrnl, r16 ; enable receiver and transmitter ldi r16, (1< 202 4921e?auto?09/09 ata6602/ata6603 4.17.6.1 receiving frames with 5 to 8 data bits the receiver starts data reception when it detects a valid start bit. each bit that follows the start bit will be sampled at the baud rate or xckn cl ock, and shifted into the receive shift register until the first stop bit of a frame is received. a second stop bit will be ignored by the receiver. when the first stop bit is received, i.e., a complete serial frame is present in the receive shift register, the contents of the shift register will be moved into the rece ive buffer. the receive buffer can then be read by reading the udrn i/o location. the following code example shows a simple us art receive function based on polling of the receive complete (rxcn) flag. when using frames with less than eight bits the most significant bits of the data read from the udrn will be masked to zero. th e usart has to be initialized before the function can be used. note: 1. the example code assumes that the pa rt specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ? sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. the function simply waits for data to be present in the receive buffer by checking the rxcn flag, before reading the buffer and returning the value. 4.17.6.2 receiving frames with 9 data bits if 9-bit characters are used (ucszn=7) the ninth bit must be read from the rxb8n bit in ucsrnb before reading the low bits from the udrn . this rule applies to the fen, dorn and upen status flags as well. read status fr om ucsrna, then data from udrn. reading the udrn i/o location will change the state of the re ceive buffer fifo and consequently the txb8n, fen, dorn and upen bits, which a ll are stored in the fifo, will change. assembly code example (1) usart_receive: ; wait for data to be received sbis ucsrna, rxcn rjmp usart_receive ; get and return received data from buffer in r16, udrn ret c code example (1) unsigned char usart_receive( void ) { /* wait for data to be received */ while ( !(ucsrna & (1< 204 4921e?auto?09/09 ata6602/ata6603 the receive function example reads all the i/o r egisters into the register file before any com- putation is done. this gives an optimal receive buffer utilization since the bu ffer location read will be free to accept new data as early as possible. 4.17.6.3 receive compete flag and interrupt the usart receiver has one flag that indicates the receiver state. the receive complete (rxcn) flag indicates if there are unread data present in the receive buf- fer. this flag is one when unread data exist in the receive buffer, and zero when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled (rxenn = 0), the receive buffer will be flushed and cons equently the rxcn bit will become zero. when the receive complete interrupt enable (r xcien) in ucsrnb is set, the usart receive complete interrupt will be executed as long as the rxcn flag is se t (provided that global inter- rupts are enabled). when interrupt-driven data reception is used, the receive complete routine must read the received data from udrn in order to clear the rxcn flag, otherwise a new inter- rupt will occur once the inte rrupt routine terminates. 4.17.6.4 receiver error flags the usart receiver has three error flags: frame error (fen), data overrun (dorn) and parity error (upen). all can be accessed by reading ucsrna. common for the error flags is that they are located in the receive buffer together with the frame for which they indicate the error status. due to the buffering of the error flags, the ucsrna must be read before the receive buffer (udrn), since reading the udrn i/o location change s the buffer read location. another equality for the error flags is that they can not be altered by software doing a write to the flag location. however, all flags must be set to zero when the ucsrna is written for upward compatibility of future usart impl ementations. none of the error flags can genera te interrupts. the frame error (fen) flag indicates the state of the first stop bit of the next readable frame stored in the receive buffer. the fen flag is zero when the stop bit was correctly read (as one), and the fen flag will be one when the stop bit was incorrect (zero). this flag can be used for detecting out-of-sync conditions, detecting break conditions and protocol handling. the fen flag is not affected by the setting of the u sbsn bit in ucsrnc since the receiver ignores all, except for the first, stop bits. for compatibility with future devices, always set this bit to zero when writing to ucsrna. the data overrun (dorn) flag indicates data loss due to a receiver buffer full condition. a data overrun occurs when the receive buffer is full (two characters), it is a new character wait- ing in the receive shift register, and a new start bit is detected. if the dorn flag is set there was one or more serial frame lost between the frame last read from udrn, and the next frame read from udrn. for compatibility wi th future devices, always write this bit to zero when writing to ucsrna. the dorn flag is cleared when t he frame received was successfully moved from the shift register to the receive buffer. the parity error (upen) flag indicates that the next frame in the receive buffer had a parity error when received. if parity check is not enabled the upen bit will always be read zero. for compatibility with future devices, always set this bit to zero when writing to ucsrna. for more details see ?parity bit calculation? on page 197 and ?parity checker? on page 205 . 205 4921e?auto?09/09 ata6602/ata6603 4.17.6.5 parity checker the parity checker is active when the high usart parity mode (upmn1) bit is set. type of par- ity check to be performed (odd or even) is selected by the upmn0 bit. when enabled, the parity checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. the result of the check is stored in the receive buffer together with the received data and stop bits. the parity error (upen) flag can then be read by software to check if the frame had a parity error. the upen bit is set if the next character that can be read from the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. 4.17.6.6 disabling the receiver in contrast to the transmitter, disabling of the receiver will be immediate. data from ongoing receptions will therefore be lost. when disabled (i .e., the rxenn is set to zero) the receiver will no longer override the normal function of the rxdn port pin. the receiver buffer fifo will be flushed when the receiver is disabled. remaining data in the buffer will be lost 4.17.6.7 flushing the receive buffer the receiver buffer fifo will be fl ushed when the receiver is disa bled, i.e., the buffer will be emptied of its contents. unread data will be lost. if the buffer has to be flushed during normal operation, due to for in stance an error conditi on, read the udrn i/o location until the rxcn flag is cleared. the following code example shows how to flush the receive buffer. note: 1. the example code assumes that the pa rt specific header file is included. for i/o registers located in extended i/o map, ?in?, ?out?, ?sbis?, ? sbic?, ?cbi?, and ?sbi? instructions must be replaced with instructi ons that allow access to extended i/o. typically ?lds? and ?sts? combined with ?sbr s?, ?sbrc?, ?sbr?, and ?cbr?. assembly code example (1) usart_flush: sbis ucsrna, rxcn ret in r16, udrn rjmp usart_flush c code example (1) void usart_flush( void ) { unsigned char dummy; while ( ucsrna & (1< 207 4921e?auto?09/09 ata6602/ata6603 figure 4-74. sampling of data and parity bit the decision of the logic level of the received bit is taken by doing a majori ty voting of the logic value to the three samples in the center of the received bit. the center samples are emphasized on the figure by having the sample number inside boxes. the majority voting process is done as follows: if two or all three samples have high levels, the received bit is registered to be a logic 1. if two or all three samples have low levels, the received bit is registered to be a logic 0. this majority voting process acts as a low pass filter for the incoming signal on the rxdn pin. the recovery process is then repeated until a complete frame is received. including the first stop bit. note that the receiver only uses the first stop bit of a frame. figure 4-75 shows the sampling of the stop bit and the earliest possible beginning of the start bit of the next frame. figure 4-75. stop bit sampling and ne xt start bit sampling the same majority voting is done to the stop bit as done for the other bits in the frame. if the stop bit is registered to have a logic 0 va lue, the frame error (fen) flag will be set. a new high to low transition indicating the start bit of a new frame can come right after the last of the bits used for majority voting. for normal speed mode, the first low level sample can be at point marked (a) in figure 4-75 . for double speed mode the first low level must be delayed to (b). (c) marks a stop bit of full length. the ear ly start bit detection influences the operational range of the receiver. 1234567 8 9 10 11 12 13 14 15 16 1 bit n 123 4 5 678 1 rxd sample (u2x = 0) sample (u2x = 1) 1234567 8 9 10 0/1 0/1 0/1 stop 1 123 4 5 6 0/1 rxd sample (u2x = 0) sample (u2x = 1) (a) (b) (c) 208 4921e?auto?09/09 ata6602/ata6603 4.17.7.3 asynchronous operational range the operational range of the receiver is dependent on the mismatch between the received bit rate and the internally generated baud rate. if the transmitter is sending frames at too fast or too slow bit rates, or the internally generated baud rate of the receiver does not have a similar (see table 4-72 ) base frequency, the receiver will not be abl e to synchronize the frames to the start bit. the following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate. d sum of character size and parity size (d = 5 to 10 bit) s samples per bit. s = 16 for normal speed mode and s = 8 for double speed mode. s f first sample number used for majority voting. s f = 8 for normal speed and s f = 4 for double speed mode. s m middle sample number used for majority voting. s m = 9 for normal speed and s m = 5 for double speed mode. r slow is the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate. r fast is the ratio of the fastest incoming data rate that can be accepted in relation to the receiver baud rate. table 4-72 and table 4-73 on page 209 list the maximum receiver baud rate error that can be tolerated. note that normal speed mode has higher toleration of baud rate variations. table 4-72. recommended maximum receiver baud rate error for normal speed mode (u2xn = 0) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 93.20 106.67 +6.67/-6.8 3.0 6 94.12 105.79 +5.79/-5.88 2.5 7 94.81 105.11 +5.11/-5.19 2.0 8 95.36 104.58 +4.58/-4.54 2.0 9 95.81 104.14 +4.14/-4.19 1.5 10 96.17 103.78 +3.78/-3.83 1.5 r slow d 1 + () s s 1 ? ds s f ++ --------------------------------------------- = r fast d 2 + () s d 1 + () ss m + ----------------------------------- = 209 4921e?auto?09/09 ata6602/ata6603 the recommendations of the maximum receiver baud rate error was made under the assump- tion that the receiver and transmitter equally divides the maximum total error. there are two possible sources fo r the receivers baud rate erro r. the receiver?s system clock (xtal) will always have some minor instabilit y over the supply voltage range and the tempera- ture range. when using a crystal to generate the system clock, this is rarely a problem, but for a resonator the system clock may differ more than 2% depending of the resonators tolerance. the second source for the error is more controllable. the baud rate generator can not always do an exact division of the system frequency to get the baud rate wanted. in th is case an ubrrn value that gives an acceptable low error can be used if possible. 4.17.8 multi-processor communication mode setting the multi-processor communication m ode (mpcmn) bit in ucsrna enables a filtering function of incoming frames received by the usart receiver. frames that do not contain address information will be ignored and not put in to the receive buffer. this effectively reduces the number of incoming frames that has to be handled by the cpu, in a system with multiple mcus that communicate via the same serial bu s. the transmitter is unaffected by the mpcmn setting, but has to be used diffe rently when it is a part of a system utilizing the multi-processor communication mode. if the receiver is set up to receive frames that contain 5 to 8 data bits, then the first stop bit indi- cates if the frame contains data or address information. if the receiver is set up for frames with nine data bits, then the ninth bit (rxb8n) is used for identifying address and data frames. when the frame type bit (the first stop or the ninth bit) is one, the frame contains an address. when the frame type bit is zero the frame is a data frame. the multi-processor communication mode enables several slave mcus to receive data from a master mcu. this is done by first decoding an address frame to find out which mcu has been addressed. if a particular slave mcu has been addressed, it will rece ive the following data frames as normal, while the other slave mcus will ignore the received frames until another address frame is received. table 4-73. recommended maximum receiver baud rate error for double speed mode (u2xn = 1) d # (data+parity bit) r slow (%) r fast (%) max total error (%) recommended max receiver error (%) 5 94.12 105.66 +5.66/-5.88 2.5 6 94.92 104.92 +4.92/-5.08 2.0 7 95.52 104,35 +4.35/-4.48 1.5 8 96.00 103.90 +3.90/-4.00 1.5 9 96.39 103.53 +3.53/-3.61 1.5 10 96.70 103.23 +3.23/-3.30 1.0 210 4921e?auto?09/09 ata6602/ata6603 4.17.8.1 using mpcmn for an mcu to act as a master mcu, it can use a 9-bit character frame format (ucszn = 7). the ninth bit (txb8n) must be set when an address frame (txb8n = 1) or cleared when a data frame (txb = 0) is being transmitted. the slave mcus must in this case be set to use a 9-bit character frame format. the following procedure should be used to exchange data in multi-processor communication mode: 1. all slave mcus are in multi-proc essor communication mode (mpcmn in ucsrna is set). 2. the master mcu sends an address frame, and all slaves receive and read this frame. in the slave mcus, the rxcn flag in ucsrna will be set as normal. 3. each slave mcu reads the udrn register and determines if it has been selected. if so, it clears the mpcmn bit in ucsrna, otherwise it waits for the next address byte and keeps the mpcmn setting. 4. the addressed mcu will receive all data fram es until a new address frame is received. the other slave mcus, which still have the mp cmn bit set, will ignore the data frames. 5. when the last data frame is received by the addressed mcu, the addressed mcu sets the mpcmn bit and waits for a new address frame from master. the process then repeats from 2. using any of the 5- to 8-bit character frame formats is possible, but impractical since the receiver must change between using n and n+1 character frame formats. this makes full-duplex operation difficult since the transmi tter and receiver uses the same character size setting. if 5- to 8-bit character frames are used, the transmitter must be set to use two stop bit (usbsn = 1) since the first stop bit is used for indicating the frame type. do not use read-modify-write in structions (sbi and cbi) to set or clear the mpcmn bit. the mpcmn bit shares the same i/o location as the txcn flag and this might accidentally be cleared when using sbi or cbi instructions. 4.17.9 usart register description 4.17.9.1 usart i/o data register n? udrn the usart transmit data buffer register and usart receive data buffer registers share the same i/o address re ferred to as usart data register or udrn. the transmit data buffer reg- ister (txb) will be the destination for data wri tten to the udrn register location. reading the udrn register location will retu rn the contents of the receiv e data buffer register (rxb). for 5-, 6-, or 7-bit char acters the upper unu sed bits will be ignored by the transmitter and set to zero by the receiver. bit 76543210 rxb[7:0] udrn (read) txb[7:0] udrn (write) read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 211 4921e?auto?09/09 ata6602/ata6603 the transmit buffer can only be written when the udren flag in the ucsrna register is set. data written to udrn wh en the udren flag is not set, will be ignored by the usart transmit- ter. when data is written to the transmit buffer, and the transmitter is enabled, the transmitter will load the data into the transmit shift regist er when the shift register is empty. then the data will be serially transmitted on the txdn pin. the receive buffer consists of a two level fifo . the fifo will change its state whenever the receive buffer is accessed. due to this behavior of the receive buffer, do not use read-mod- ify-write instructions (sbi and cb i) on this location. be careful when using bit test instructions (sbic and sbis), since these also will change the state of the fifo. 4.17.9.2 usart control and status register n a ? ucsrna ? bit 7 ? rxcn: usart receive complete this flag bit is set when there are unread data in the receive buffer and cleared when the receive buffer is empty (i.e., does not contain any unread data). if the receiver is disabled, the receive buffer will be flushed and consequently the rxcn bit will become zero. the rxcn flag can be used to generate a receive complete interrupt (see description of the rxcien bit). ? bit 6 ? txcn: usart transmit complete this flag bit is set when the entire frame in the transmit shift register has been shifted out and there are no new data currently present in the transmit buffer (udrn). the txcn flag bit is automatically cleared when a transmit complete interrupt is executed, or it can be cleared by writing a one to its bit location. the txcn flag can generate a transmit com- plete interrupt (see description of the txcien bit). ? bit 5 ? udren: usart data register empty the udren flag indicates if the transmit buffer (udrn) is ready to receive new data. if udren is one, the buffer is em pty, and therefore ready to be written. the udren flag can generate a data register empty interrupt (see description of the udrien bit). udren is set after a reset to indicate that the transmitter is ready. ? bit 4 ? fen: frame error this bit is set if the next character in the receive buffer had a frame error when received. i.e., when the first stop bit of the next characte r in the receive buffer is zero. this bit is valid until the receive buffer (udrn) is read. the fen bit is zero when the stop bit of received data is one. always set this bit to zero when writing to ucsrna. ? bit 3 ? dorn: data overrun this bit is set if a data overrun condition is detected. a data overrun occurs when the receive buffer is full (two char acters), it is a new character waiting in the receive shift reg- ister, and a new start bit is det ected. this bit is valid until th e receive buffer (udrn) is read. always set this bit to ze ro when writing to ucsrna. bit 76543210 rxcn txcn udren fen dorn upen u2xn mpcmn ucsrna read/write r r/w r r r r r/w r/w initial value 0 0 1 0 0 0 0 0 212 4921e?auto?09/09 ata6602/ata6603 ? bit 2 ? upen: usart parity error this bit is set if the next character in the receive buffer had a parity error when received and the parity checking was enabled at that point (upmn1 = 1). this bit is valid until the receive buffer (udrn) is read. always set this bit to zero when writing to ucsrna. ? bit 1 ? u2xn: double the usart transmission speed this bit only has effect for the asynchronous operation. write this bit to zero when using syn- chronous operation. writing this bit to one will reduce the divisor of the baud rate divider from 16 to 8 effectively doubling the transfer rate for asynchronous communication. ? bit 0 ? mpcmn: multi-processor communication mode this bit enables the multi-processor communi cation mode. when the mpcmn bit is written to one, all the incoming frames received by the usart receiver that do not contain address information will be ignored. the transmitter is unaffected by the mpcmn setting. for more detailed information see ?multi-processor communication mode? on page 209 . 4.17.9.3 usart control and status register n b ? ucsrnb ? bit 7 ? rxcien: rx complete interrupt enable n writing this bit to one enables interrupt on the rxcn flag. a usart receive complete interrupt will be generated on ly if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. ? bit 6 ? txcien: tx complete interrupt enable n writing this bit to one enables interrupt on the txcn flag. a usart transmit complete interrupt will be genera ted only if the txcien bit is writt en to one, the glob al interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. ? bit 5 ? udrien: usart data regi ster empty interrupt enable n writing this bit to one enables interrupt on the udren flag. a data register empty interrupt will be generated only if the udrien bit is written to one, t he global in terrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 ? rxenn: receiver enable n writing this bit to one enables the usart re ceiver. the receiver will override normal port operation for the rxdn pin when enabled. disab ling the receiver will flush the receive buffer invalidating the fen, dorn, and upen flags. ? bit 3 ? txenn: transmitter enable n writing this bit to one enables the usart tr ansmitter. the transmi tter will override normal port operation for the txdn pin when enabled. the disabling of the transmitter (writing txenn to zero) will not become effective unt il ongoing and pending transmissions are com- pleted, i.e., when the transmit shift register and transmit buffer register do not contain data to be transmitted. when di sabled, the transmitter will no lo nger override t he txdn port. bit 7 6 5 4 3 2 1 0 rxcien txcien udrien rxenn txenn ucszn2 rxb8n txb8n ucsrnb read/write r/w r/w r/w r/w r/w r/w r r/w initial value 0 0 0 0 0 0 0 0 213 4921e?auto?09/09 ata6602/ata6603 ? bit 2 ? ucszn2: character size n the ucszn2 bits combined with the ucszn1:0 bit in ucsrnc sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 1 ? rxb8n: receive data bit 8 n rxb8n is the ninth data bit of the received character when operating with serial frames with nine data bits. must be read before reading the low bits from udrn. ? bit 0 ? txb8n: transmit data bit 8 n txb8n is the ninth data bit in the characte r to be transmitted when operating with serial frames with nine data bits. must be writ ten before writing th e low bits to udrn. 4.17.9.4 usart control and status register n c ? ucsrnc ? bits 7:6 ? umseln1:0 usart mode select these bits select the mode of operation of the usartn as shown in table 4-74 . note: 1. see ?usart in spi mode? on page 218 for full description of the master spi mode (mspim) operation ? bits 5:4 ? upmn1:0: parity mode these bits enable and set type of parity ge neration and check. if enabled, the transmitter will automatically generate and send the parity of the transmitted data bits within each frame. the receiver will generate a parity value for the inco ming data and compare it to the upmn setting. if a mismat ch is detected, the upen flag in ucsrna will be set. ? bit 3 ? usbsn: stop bit select this bit selects the number of stop bits to be inserted by the transmitter. the receiver ignores this setting. bit 7 6 5 4 3 2 1 0 umseln1 umseln0 upmn1 upmn0 usbsn ucszn1 ucszn0 ucpoln ucsrnc read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value 0 0 0 0 0 1 1 0 table 4-74. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reserved) 1 1 master spi (mspim) (1) table 4-75. upmn bits settings upmn1 upmn0 parity mode 0 0 disabled 01reserved 1 0 enabled, even parity 1 1 enabled, odd parity 214 4921e?auto?09/09 ata6602/ata6603 ? bit 2:1 ? ucszn1:0: character size the ucszn1:0 bits combined with the ucszn2 bit in ucsrnb sets the number of data bits (character size) in a frame the receiver and transmitter use. ? bit 0 ? ucpoln: clock polarity this bit is used for synchronous mode only. write this bit to zero when asynchronous mode is used. the ucpoln bit sets the relationship between data output change and data input sample, and th e synchronous clock (xckn). table 4-76. usbs bit settings usbsn stop bit(s) 01-bit 12-bit table 4-77. ucszn bits settings ucszn2 ucszn1 ucszn0 character size 0005-bit 0016-bit 0107-bit 0118-bit 1 0 0 reserved 1 0 1 reserved 1 1 0 reserved 1119-bit table 4-78. ucpoln bit settings ucpoln transmitted data changed (output of txdn pin) received data sampled (input on rxdn pin) 0 rising xckn edge falling xckn edge 1 falling xckn edge rising xckn edge 215 4921e?auto?09/09 ata6602/ata6603 4.17.9.5 usart baud rate registers ? ubrrnl and ubrrnh ? bit 15:12 ? reserved bits these bits are reserved for future use. for compatibility with future devices, these bit must be written to zero when ubrrnh is written. ? bit 11:0 ? ubrr11:0: usart baud rate register this is a 12-bit register which contains t he usart baud rate. the ubrrnh contains the four most significant bits, and the ubrrnl contains the eight least significant bits of the usart baud rate. ongoing transmissions by the tran smitter and receiv er will be corrupted if the baud rate is changed. writing ubrrnl will trigger an immediate update of the baud rate prescaler. 4.17.10 examples of baud rate setting for standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the ubrrn settings in table 4-79 on page 216 . ubrrn values which yield an actual baud rate differing less than 0.5% from the target baud rate, are bold in the table. higher error ratings are acceptable, but the receiver will have less noise resistance when the error ratings are high, especially for large serial frames (see ?asyn- chronous operational range? on page 208 ). the error values are calculated using the following equation: bit 151413121110 9 8 ? ? ? ? ubrrn[11:8] ubrrnh ubrrn[7:0] ubrrnl 76543210 read/write rrrrr/wr/wr/wr/w r/w r/w r/w r/w r/w r/w r/w r/w initial value 00000000 00000000 error[%] baudrate closest match baudrate -------------------------------------------------------- 1 ? ?? ?? 100% ? = 216 4921e?auto?09/09 ata6602/ata6603 note: 1. ubrrn = 0, error = 0.0% table 4-79. examples of ubrrn settings for co mmonly used oscillator frequencies baud rate (bps) f osc = 1.0000 mhz f osc = 1.8432 mhz f osc = 2.0000 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 25 0.2% 51 0.2% 47 0.0% 95 0.0% 51 0.2% 103 0.2% 4800 12 0.2% 25 0.2% 23 0.0% 47 0.0% 25 0.2% 51 0.2% 9600 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 12 0.2% 25 0.2% 14.4k 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 19.2k 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 28.8k 1 8.5% 3 8.5% 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 38.4k 1 -18.6% 2 8.5% 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 57.6k 0 8.5% 1 8.5% 1 0.0% 3 0.0% 1 8.5% 3 8.5% 76.8k ? ? 1 -18.6% 1 -25.0% 2 0.0% 1 -18.6% 2 8.5% 115.2k ? ? 0 8.5% 0 0.0% 1 0.0% 0 8.5% 1 8.5% 230.4k??????00.0%???? 250k ??????????00.0% max. (1) 62.5 kbps 125 kbps 115.2 kbps 2 30.4 kbps 125 kbps 250 kbps table 4-80. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 3.6864 mhz f osc = 4.0000 mhz f osc = 7.3728 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 95 0.0% 191 0.0% 103 0.2% 207 0.2% 191 0.0% 383 0.0% 4800 47 0.0% 95 0.0% 51 0.2% 103 0.2% 95 0.0% 191 0.0% 9600 23 0.0% 47 0.0% 25 0.2% 51 0.2% 47 0.0% 95 0.0% 14.4k 15 0.0% 31 0.0% 16 2.1% 34 -0.8% 31 0.0% 63 0.0% 19.2k 110.0%230.0%120.2%250.2%230.0%470.0% 28.8k 7 0.0% 15 0.0% 8 -3.5% 16 2.1% 15 0.0% 31 0.0% 38.4k 5 0.0% 11 0.0% 6 -7.0% 12 0.2% 11 0.0% 23 0.0% 57.6k 3 0.0% 7 0.0% 3 8.5% 8 -3.5% 7 0.0% 15 0.0% 76.8k 2 0.0% 5 0.0% 2 8.5% 6 -7.0% 5 0.0% 11 0.0% 115.2k 1 0.0% 3 0.0% 1 8.5% 3 8.5% 3 0.0% 7 0.0% 230.4k 0 0.0% 1 0.0% 0 8.5% 1 8.5% 1 0.0% 3 0.0% 250k 0 -7.8% 1 -7.8% 0 0.0% 1 0.0% 1 -7.8% 3 -7.8% 0.5m ? ? 0 -7.8% ? ? 0 0.0% 0 -7.8% 1 -7.8% 1m ??????????0-7.8% max. (1) 230.4 kbps 460.8 kbps 250 kbps 0.5 mbps 460.8 kbps 921.6 kbps 1. ubrrn = 0, error = 0.0% 217 4921e?auto?09/09 ata6602/ata6603 table 4-81. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 8.0000 mhz f osc = 11.0592 mhz f osc = 14.7456 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 207 0.2% 416 -0.1% 287 0.0% 575 0.0% 383 0.0% 767 0.0% 4800 103 0.2% 207 0.2% 143 0.0% 287 0.0% 191 0.0% 383 0.0% 9600 51 0.2% 103 0.2% 71 0.0% 143 0.0% 95 0.0% 191 0.0% 14.4k 34 -0.8% 68 0.6% 47 0.0% 95 0.0% 63 0.0% 127 0.0% 19.2k 250.2%510.2%350.0%710.0%470.0%950.0% 28.8k 16 2.1% 34 -0.8% 23 0.0% 47 0.0% 31 0.0% 63 0.0% 38.4k 120.2%250.2%170.0%350.0%230.0%470.0% 57.6k 8 -3.5% 16 2.1% 11 0.0% 23 0.0% 15 0.0% 31 0.0% 76.8k 6 -7.0% 12 0.2% 8 0.0% 17 0.0% 11 0.0% 23 0.0% 115.2k 3 8.5% 8 -3.5% 5 0.0% 11 0.0% 7 0.0% 15 0.0% 230.4k 1 8.5% 3 8.5% 2 0.0% 5 0.0% 3 0.0% 7 0.0% 250k 1 0.0% 3 0.0% 2 -7.8% 5 -7.8% 3 -7.8% 6 5.3% 0.5m 0 0.0% 1 0.0% ? ? 2 -7.8% 1 -7.8% 3 -7.8% 1m ? ? 0 0.0% ? ? ? ? 0 -7.8% 1 -7.8% max. (1) 0.5 mbps 1 mbps 691.2 kbps 1.3824 mbps 921.6 kbps 1.8432 mbps 1. ubrrn = 0, error = 0.0% table 4-82. examples of ubrrn settings for common ly used oscillator frequencies (continued) baud rate (bps) f osc = 16.0000 mhz f osc = 18.4320 mhz f osc = 20.0000 mhz u2xn = 0u2xn = 1u2xn = 0u2xn = 1u2xn = 0u2xn = 1 ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error ubrrn error 2400 416 -0.1% 832 0.0% 479 0.0% 959 0.0% 520 0.0% 1041 0.0% 4800 207 0.2% 416 -0.1% 239 0.0% 479 0.0% 259 0.2% 520 0.0% 9600 103 0.2% 207 0.2% 119 0.0% 239 0.0% 129 0.2% 259 0.2% 14.4k 68 0.6% 138 -0.1% 79 0.0% 159 0.0% 86 -0.2% 173 -0.2% 19.2k 51 0.2% 103 0.2% 59 0.0% 119 0.0% 64 0.2% 129 0.2% 28.8k 34 -0.8% 68 0.6% 39 0.0% 79 0.0% 42 0.9% 86 -0.2% 38.4k 25 0.2% 51 0.2% 29 0.0% 59 0.0% 32 -1.4% 64 0.2% 57.6k 16 2.1% 34 -0.8% 19 0.0% 39 0.0% 21 -1.4% 42 0.9% 76.8k 120.2%250.2%140.0%290.0%151.7%32-1.4% 115.2k 8 -3.5% 16 2.1% 9 0.0% 19 0.0% 10 -1.4% 21 -1.4% 230.4k 3 8.5% 8 -3.5% 4 0.0% 9 0.0% 4 8.5% 10 -1.4% 250k 3 0.0% 7 0.0% 4 -7.8% 8 2.4% 4 0.0% 9 0.0% 0.5m 1 0.0% 3 0.0% ? ? 4 -7.8% ? ? 4 0.0% 1m 00.0%10.0%???????? max. (1) 1 mbps 2 mbps 1.152 mbps 2.3 04 mbps 1.25 mbps 2.5 mbps 1. ubrrn = 0, error = 0.0% 218 4921e?auto?09/09 ata6602/ata6603 4.18 usart in spi mode the universal synchronous and asynchronous serial receiver and transmitter (usart) can be set to a master spi compliant mode of operation. the master spi mode (mspim) has the follow- ing features: ? full duplex, three-wire synchronous data transfer ? master operation ? supports all four spi modes of operation (mode 0, 1, 2, and 3) ? lsb first or msb first data tran sfer (configurable data order) ? queued operation (double buffered) ? high resolution baud rate generator ? high speed operat ion (fxckmax = f ck /2) ? flexible interrupt generation 4.18.1 overview setting both umseln1:0 bits to one enables the usart in mspim logic. in this mode of opera- tion the spi master control logic takes direct control over the usart resources. these resources include the transmitter and receiver shift register and buffers, and the baud rate gen- erator. the parity generator and checker, the data and clock recovery logic, and the rx and tx control logic is disabled. the usart rx and tx control logic is replaced by a common spi transfer control logic. however, the pin control l ogic and interrupt generation logic is identical in both modes of operation. the i/o register locations are the same in both modes. however, some of the functionality of the control registers changes when using mspim. 4.18.2 clock generation the clock generation logic generates the base clock for the transmitter and receiver. for usart mspim mode of operation only internal cl ock generation (i.e. master operation) is sup- ported. the data direction register for the xckn pin (ddr_xckn) must therefore be set to one (i.e. as output) for th e usart in mspim to operate correc tly. preferably the ddr_xckn should be set up before the usart in mspim is enabled (i.e. txenn and rxenn bit set to one). the internal clock generation used in mspim mode is identical to the usart synchronous mas- ter mode. the baud rate or ubrrn setting can therefore be calculated using the same equations (see table 4-83 on page 219 ). 219 4921e?auto?09/09 ata6602/ata6603 note: 1. the baud rate is defined to be the transfer rate in bit per second (bps) baud baud rate (in bits per second, bps) f osc system oscillator clock frequency ubrrn contents of the ubrrnh and ubrrnl registers, (0-4095) 4.18.3 spi data modes and timing there are four combinations of xckn (sck) phase and polarity with respect to serial data, which are determined by control bits ucphan and ucpoln. the data transfer timing diagrams are shown in figure 4-76 on page 219 . data bits are shifted out and latched in on opposite edges of the xckn signal, ensuring sufficient time for data signals to stabilize. the ucpoln and ucphan functionality is summarized in table 4-84 . note that changing the setting of any of these bits will corrupt all ongoing communication for both the receiver and transmitter. figure 4-76. ucphan and ucpoln data transfer timing diagrams table 4-83. equations for calculating baud rate register setting operating mode equation for calculating baud rate (1) equation for calculating ubrrn value synchronous master mode baud f osc 2 ubrr n 1 + () -------------------------------------- - = ubrr n f osc 2 baud -------------------- 1 ? = table 4-84. ucpoln and ucphan functionality- ucpoln ucphan spi mode lead ing edge trailing edge 0 0 0 sample (rising) setup (falling) 0 1 1 setup (rising) sample (falling) 1 0 2 sample (falling) setup (rising) 1 1 3 setup (falling) sample (rising) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) xck data setup (txd) data sample (rxd) ucpol=0 ucpol=1 ucpha=0 ucpha=1 220 4921e?auto?09/09 ata6602/ata6603 4.18.4 frame formats a serial frame for the mspim is defined to be one character of 8 data bits. the usart in mspim mode has two valid frame formats: ? 8-bit data with msb first ? 8-bit data with lsb first a frame starts with the least or most significant data bit. then the next data bits, up to a total of eight, are succeeding, ending with the most or least significant bit accordingly. when a complete frame is transmitted, a new frame can directly follow it, or the communication line can be set to an idle (high) state. the udordn bit in ucsrnc sets the frame form at used by the usart in mspim mode. the receiver and transmitter use the same setting. note that changing the setting of any of these bits will corrupt all ongoin g communication for both th e receiver and transmitter. 16-bit data transfer can be achieved by writing two data bytes to udrn. a uart transmit com- plete interrupt will then signal that the 16-bit value ha s been shifted out. 4.18.4.1 usart mspim initialization the usart in mspim mode has to be initialized before any communication can take place. the initialization process normally consists of setting the baud rate, setting master mode of operation (by setting ddr_xckn to one), setting frame format and enabling the transmitter and the receiver. only the transmitter can operate independently. for interrupt driven usart opera- tion, the global interrupt flag should be clear ed (and thus interrupts globally disabled) when doing the initialization. note: to ensure immediate initialization of the xckn output the baud-rate register (ubrrn) must be zero at the time the transmitter is enabled. contrary to the normal mode usart operation the ubrrn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. setting ubrrn to ze ro before enabling the transmitter is not neces- sary if the initialization is done immediatel y after a reset since ubrrn is reset to zero. before doing a re-initialization with changed baud rate, data mode, or frame format, be sure that there is no ongoing transmissions during the per iod the registers are changed. the txcn flag can be used to check that the transmitter has completed all transfers, and the rxcn flag can be used to check that there are no unread data in the receive buffer. note that the txcn flag must be cleared bef ore each transmission (before udrn is wri tten) if it is used for this purpose. the following simple usart initialization code examples show one assembly and one c func- tion that are equal in functionality. the examples assume polling (no interrupts enabled). the baud rate is given as a function parameter. for the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 registers. 221 4921e?auto?09/09 ata6602/ata6603 note: 1. the example code assumes that the part spec ific header file is included. for i/o registers located in extended i/o map, "in", "out", "sbis" , "sbic", "cbi", and "sbi" instructions must be replaced with instructions that allow access to extended i/o. typically "lds" and "sts" combined with "sbrs", "sbr c", "sbr", and "cbr". assembly code example (1) usart_init: clr r18 out ubrrnh,r18 out ubrrnl,r18 ; setting the xckn port pin as output, enables master mode. sbi xckn_ddr, xckn ; set mspi mode of operation and spi data mode 0. ldi r18, (1< 223 4921e?auto?09/09 ata6602/ata6603 note: 1. the example code assumes that the part spec ific header file is included. for i/o registers located in extended i/o map, "in", "out", "sbis" , "sbic", "cbi", and "sbi" instructions must be replaced with instructions that allow access to extended i/o. typically "lds" and "sts" combined with "sbrs", "sbr c", "sbr", and "cbr". 4.18.5.1 transmitter and receiver flags and interrupts the rxcn, txcn, and udren flag s and corresponding interrupt s in usart in mspim mode are identical in function to the normal usart operation. however, the receiver error status flags (fe, dor, and pe) are not in use and is always read as zero. 4.18.5.2 disabling the transmitter or receiver the disabling of the transmitter or receiver in usart in mspim mode is identical in function to the normal usart operation. assembly code example (1) usart_mspim_transfer: ; wait for empty transmit buffer sbis ucsrna, udren rjmp usart_mspim_transfer ; put data (r16) into buffer, sends the data out udrn,r16 ; wait for data to be received usart_mspim_wait_rxcn: sbis ucsrna, rxcn rjmp usart_mspim_wait_rxcn ; get and return received data from buffer in r16, udrn ret c code example (1) unsigned char usart_receive( void ) { /* wait for empty transmit buffer */ while ( !( ucsrna & (1< 225 4921e?auto?09/09 ata6602/ata6603 4.18.6.3 usart mspim control and status register n b - ucsrnb ? bit 7 - rxcien: rx complete interrupt enable writing this bit to one enables interrupt on the rxcn flag. a usart receive complete interrupt will be generated on ly if the rxcien bit is written to one, the global interrupt flag in sreg is written to one and the rxcn bit in ucsrna is set. ? bit 6 - txcien: tx complete interrupt enable writing this bit to one enables interrupt on the txcn flag. a usart transmit complete interrupt will be genera ted only if the txcien bit is writt en to one, the glob al interrupt flag in sreg is written to one and the txcn bit in ucsrna is set. ? bit 5 - udrie: usart data register empty interrupt enable writing this bit to one enables interrupt on the udren flag. a data register empty interrupt will be generated only if the udrie bit is writte n to one, the global inte rrupt flag in sreg is written to one and the udren bit in ucsrna is set. ? bit 4 - rxenn: receiver enable writing this bit to one enables the usart rece iver in mspim mode. th e receiver will over- ride normal port operat ion for the rxdn pin when enabled. disabling the receiver will flush the receive buffer. only enabling the receiver in mspi mode (i.e. setting rxenn=1 and txenn=0) has no meaning since it is the transmitter that controls the transfer clock and since only master mode is supported. ? bit 3 - txenn: transmitter enable writing this bit to one enables the usart tr ansmitter. the transmi tter will override normal port operation for the txdn pin when enabled. the disabling of the transmitter (writing txenn to zero) will not become effective unt il ongoing and pending transmissions are com- pleted, i.e., when the transmit shift register and transmit buffer register do not contain data to be transmitted. when di sabled, the transmitter will no lo nger override t he txdn port. ? bit 2:0 - reserved bits in mspi mode when in mspi mode, these bits are reserved for future use. for compatibility with future devices, these bits must be written to zero when ucsrnb is written. bit 7 6543210 rxcien txcien udrie rxenn txenn - - - ucsrnb read/write r/w r/w r/w r/w r/w r r r initial value 0 0 0 0 0 1 1 0 226 4921e?auto?09/09 ata6602/ata6603 4.18.6.4 usart mspim control and status register n c - ucsrnc ? bit 7:6 - umseln1:0: usart mode select these bits select the mode of oper ation of the usart as shown in table 4-85 . see ?usart control and status register n c ? ucsrnc? on page 213 for full description of the normal usart operation. the mspim is enabled when both umseln bits are set to one. the udordn, ucphan, and ucpoln can be set in the same write operation where the mspim is enabled. ? bit 5:3 - reserved bits in mspi mode when in mspi mode, these bits are reserved for future use. for compatibility with future devices, these bits must be written to zero when ucsrnc is written. ? bit 2 - udordn: data order when set to one the lsb of the data word is transmitted first. when set to zero the msb of the data word is transmitted first. refer to the section ?frame formats? on page 196 for details. ? bit 1 - ucphan: clock phase the ucphan bit setting determine if data is sampled on the le asing edge (first) or tailing (last) edge of xckn. refer to the section ?spi data modes and timing? on page 219 for details. ? bit 0 - ucpoln: clock polarity the ucpoln bit sets the polarity of the xckn clock. the combination of the ucpoln and ucphan bit settings determine the timing of the data transfer. refer to the section ?spi data modes and timing? on page 219 for details. usart mspim baud rate registers - ubrrnl and ubrrnh the function and bit description of the baud rate registers in mspi mode is identical to normal usart operation (see ?usart baud rate registers ? ubrrnl and ubrrnh? on page 215 ). bit 7 6 5 4 3 2 1 0 umseln1 umseln0 - - - udordn ucphan ucpoln ucsrnc read/write r/w r/w r r r r/w r/w r/w initial value 0 0 0 0 0 1 1 0 table 4-85. umseln bits settings umseln1 umseln0 mode 0 0 asynchronous usart 0 1 synchronous usart 1 0 (reserved) 1 1 master spi (mspim) 227 4921e?auto?09/09 ata6602/ata6603 4.18.7 avr usart mspim versus avr spi the usart in mspim mode is fully co mpatible with the avr spi regarding: ? master mode timing diagram. ? the ucpoln bit functionality is identical to the spi cpol bit. ? the ucphan bit functionality is identical to the spi cpha bit. ? the udordn bit functionality is identical to the spi dord bit. however, since the usart in mspim mode reuses the usart resources, the use of the usart in mspim mode is somewhat different compared to the spi. in addition to differences of the control register bits, and that only master operation is supported by the usart in mspim mode, the following features differ between the two modules: ? the usart in mspim mode includes (double) buffering of the transmitter. the spi has no buffer. ? the usart in mspim mode receiver includes an additional buffer level. ? the spi wcol (write collis ion) bit is not included in usart in mspim mode. ? the spi double speed mode (spi2x) bit is not included. however, the same effect is achieved by setting ubrrn accordingly. ? interrupt timing is not compatible. ? pin control differs due to the master only operation of the usart in mspim mode. a comparison of the usart in mspim mode and the spi pins is shown in table 4-86 . table 4-86. comparison of usart in mspim mode and spi pins. usart_mspim spi comment txdn mosi master out only rxdn miso master in only xckn sck (functionally identical) (n/a) ss not supported by usart in mspim 228 4921e?auto?09/09 ata6602/ata6603 4.19 2-wire serial interface 4.19.1 features ? simple yet powerful and flexible communication interface, only two bus lines needed ? both master and sla ve operation supported ? device can operate as transmitter or receiver ? 7-bit address space allows up to 128 different slave addresses ? multi-master arbitration support ? up to 400 khz data transfer speed ? slew-rate limited output drivers ? noise suppression circuitry rejects spikes on bus lines ? fully programmable slave address with general call support ? address recognition causes wake-up when avr is in sleep mode 4.19.2 2-wire serial interface bus definition the 2-wire serial interface (twi) is ideally suit ed for typical microcon troller applications. the twi protocol allows the systems designer to in terconnect up to 128 diffe rent devices using only two bi-directional bus lines, one for clock (scl) and one for data (sda). the only external hard- ware needed to implement the bus is a single pull- up resistor for each of the twi bus lines. all devices connected to the bus have individual addresses, and mechanisms for resolving bus contention are inherent in the twi protocol. figure 4-77. twi bus interconnection 4.19.2.1 twi terminology the following definitions are frequently encountered in this section. the prtwi bit in ?power reduction register - prr? on page 64 must be written to zero to enable the 2-wire serial interface. device 1 device 2 device 3 device n sda scl ........ r1 r2 v cc table 4-87. twi terminology term description master the device that initiates and terminates a transmission. the master also generates the scl clock. slave the device addressed by a master. transmitter the device placing data on the bus. receiver the device reading data from the bus. 229 4921e?auto?09/09 ata6602/ata6603 4.19.2.2 electrical interconnection as depicted in figure 4-77 on page 228 , both bus lines are connected to the positive supply volt- age through pull-up resistors. the bus drivers of all twi-compliant devices are open-drain or open-collector. this implements a wired-and function which is essential to the operation of the interface. a low level on a twi bus line is generated when one or more twi devices output a zero. a high level is output when all twi devices tri-state their outputs, allowing the pull-up resis- tors to pull the line high. note that all avr devices connected to the twi bus must be powered in order to allow any bus operation. the number of devices that can be connected to the bus is only limited by the bus capacitance limit of 400 pf and the 7-bit slave address space. a detailed specification of the electrical char- acteristics of the twi is given in ?2-wire serial interface characteristics? on page 322 . two different sets of specifications are presented t here, one relevant for bus speeds below 100 khz, and one valid for bus speeds up to 400 khz. 4.19.3 data transfer and frame format 4.19.3.1 transferring bits each data bit transferred on the twi bus is accompanied by a pulse on the clock line. the level of the data line must be stable when the clock line is high. the only exception to this rule is for generating start and stop conditions. figure 4-78. data validity 4.19.3.2 start and stop conditions the master initiates and terminates a data transmi ssion. the transmission is initiated when the master issues a start condition on the bus, and it is terminated when the master issues a stop condition. between a start and a stop condition, the bus is considered busy, and no other master should try to seize control of the bus. a special case occurs when a new start condition is issued between a start and stop condition. this is referred to as a repeated start condition, and is used when the master wis hes to initiate a new transfer without relin- quishing control of the bus. after a repeated start, the bus is considered busy until the next stop. this is identical to the start behavior, and therefore start is used to describe both start and repeated start for the remainder of this datasheet, unless otherwise noted. as depicted below, start and stop conditions are signalled by changing the level of the sda line when the scl line is high. sda scl data stable data stable data chan g e 230 4921e?auto?09/09 ata6602/ata6603 figure 4-79. start, repeated start and stop conditions 4.19.3.3 address packet format all address packets transmitted on the twi bus ar e 9 bits long, consisti ng of 7 address bits, one read/write control bit and an acknowledge bit. if the read/write bit is set, a read opera- tion is to be performed, otherwise a write operation should be performed. when a slave recognizes that it is being a ddressed, it should acknowledge by pulling sda low in the ninth scl (ack) cycle. if the addressed slave is busy, or for some other reason can not service the mas- ter?s request, the sda line should be left high in the ack clock cycle. the master can then transmit a stop condition, or a repeated start condition to initiate a new transmission. an address packet consisting of a slave address and a read or a write bit is called sla+r or sla+w, respectively. the msb of the address byte is transmitted first. slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. when a general call is issued, all slaves should respond by pulling the sda line low in the ack cycle. a general call is used when a master wi shes to transmit the same message to several slaves in the system. when the general call address followed by a write bit is transmitted on the bus, all slaves set up to ackn owledge the general call will pull th e sda line low in the ack cycle. the following data packets will then be received by all the slaves that acknowle dged the general call. note that transmitting the general call add ress followed by a read bit is meaningless, as this would cause contention if several slaves started transmitting different data. all addresses of the format 1111 xxx should be reserved for future purposes. figure 4-80. address packet format sda scl start stop repeated start stop start sda scl start 12 789 addr msb addr lsb r/w ack 231 4921e?auto?09/09 ata6602/ata6603 4.19.3.4 data packet format all data packets transmitted on the twi bus are nine bits long, consisting of one data byte and an acknowledge bit. during a data transfer, the master generates the clock and the start and stop conditions, while the receiver is res ponsible for acknowledging the reception. an acknowledge (ack) is signalled by the receiver pulling the sda line low during the ninth scl cycle. if the receiver leaves the sda line high, a nack is signalled. when the receiver has received the last byte, or for some reason cannot receive any more bytes, it should inform the transmitter by sending a nack after the final byte. the msb of the data byte is transmitted first. figure 4-81. data packet format 4.19.3.5 combining address and data packets into a transmission a transmission basically consists of a start co ndition, a sla+r/w, one or more data packets and a stop condition. an empty message, consisting of a start followed by a stop condi- tion, is illegal. note that the wired-an ding of the scl line can be used to implement handshaking between the master and the slave. the slave can extend the scl low period by pulling the scl line low. this is useful if the cloc k speed set up by the master is too fast for the slave, or the slave needs extra time for proces sing between the data transmissions. the slave extending the scl low period will not affect t he scl high period, which is determined by the master. as a consequence, the slave can reduce the twi data transfer speed by prolonging the scl duty cycle. figure 4-82 shows a typical data transmission. note that several data bytes can be transmitted between the sla+r/w and the stop condition, depending on the software protocol imple- mented by the application software. figure 4-82. typical data transmission 12 789 data msb data lsb ack aggregate sda sda from transmitter sda from receiver scl from master sla+r/w data byte stop, repeated start or next data b y te 12 789 data byte data msb data lsb ack sda scl start 12 789 addr msb addr lsb r/w ack sla+r/w stop 232 4921e?auto?09/09 ata6602/ata6603 4.19.4 multi-master bus systems, arbitration and synchronization the twi protocol allows bus systems with seve ral masters. special concerns have been taken in order to ensure that transmis sions will proceed as normal, even if two or more masters initiate a transmission at the same time. two problems arise in multi-master systems: ? an algorithm must be implemented allowing only one of the masters to complete the transmission. all other masters should cease transmission when they discover that they have lost the selection process. this selection proc ess is called arbitration. when a contending master discovers that it has lost the arbitration process, it should immediately switch to slave mode to check whether it is being addressed by the winning master. the fact that multiple masters have started transmission at the same time should not be detectable to the slaves, i.e. the data being transferred on the bus must not be corrupted. ? different masters may use different scl frequencies. a scheme must be devised to synchronize the serial clocks from all masters, in order to let the transmission proceed in a lockstep fashion. this will fac ilitate the arbitration process. the wired-anding of the bus lines is used to solv e both these problems. the serial clocks from all masters will be wired-anded, yielding a co mbined clock with a high period equal to the one from the master with the shortest high period. the low period of the combined clock is equal to the low period of the master with the longest low period. note that all masters listen to the scl line, effectively starting to count their scl high and low time-out periods when the combined scl line goes high or low, respectively. figure 4-83. scl synchronization betw een multiple masters ta low ta high scl from master a scl from master b scl bus line tb low tb high masters start countin g low period masters start countin g hi g h period 233 4921e?auto?09/09 ata6602/ata6603 arbitration is carried out by all masters cont inuously monitoring the sda line after outputting data. if the value read from the sda line does not match the value the master had output, it has lost the arbitration. note that a master can only lose arbitration when it outputs a high sda value while another master outputs a low value. the losing master should immediately go to slave mode, checking if it is being addressed by the winning master. the sda line should be left high, but losing masters are allowed to generate a clock signal until the end of the current data or address packet. arbitration will cont inue until only one master re mains, and this may take many bits. if several masters are trying to address th e same slave, arbitratio n will continue into the data packet. figure 4-84. arbitration between two masters note that arbitration is not allowed between: ? a repeated start cond ition and a data bit. ? a stop condition and a data bit. ? a repeated start and a stop condition. it is the user software?s responsibility to ensur e that these illegal arbitration conditions never occur. this implies that in multi-master systems, all data transfers must use the same composi- tion of sla+r/w and data packets. in other words: all transmissions must contain the same number of data packets, otherwise the result of the arbitration is undefined. sda from master a sda from master b sda line synchronized scl line start master a loses arbitration, sda a sda 234 4921e?auto?09/09 ata6602/ata6603 4.19.5 overview of the twi module the twi module is comprised of several submodules, as shown in figure 4-85 . all registers drawn in a thick line are accessible through the avr data bus. figure 4-85. overview of the twi module 4.19.5.1 scl and sda pins these pins interface the avr twi with the rest of the mcu system. the output drivers contain a slew-rate limiter in order to conform to the twi specification. the input stages contain a spike suppression unit removing spikes shorter than 50 ns. note that the internal pull-ups in the avr pads can be enabled by setting the port bits corresponding to the scl and sda pins, as explained in the i/o port section. the internal pull-ups can in some systems eliminate the need for external ones. twi unit address register (twar) address match unit address comparator control unit control register (twcr) status register (twsr) state machine and status control scl slew-rate control spike filter sda slew-rate control spike filter bit rate generator bit rate register (twbr) prescaler bus interface unit start / stop control arbitration detection ack spike suppression address/data shift register (twdr) 235 4921e?auto?09/09 ata6602/ata6603 4.19.5.2 bit rate generator unit this unit controls the period of scl when oper ating in a master mode. the scl period is con- trolled by settings in the twi bit rate register (twbr) and the prescaler bits in the twi status register (twsr). slave operation does not depend on bit rate or prescaler settings, but the cpu clock frequency in the slave must be at l east 16 times higher than the scl frequency. note that slaves may prolong the scl low period, thereby reducing the average twi bus clock period. the scl frequency is generated according to the following equation: ? twbr = value of the twi bit rate register. ? prescalervalue = value of the prescaler (see table 4-88 on page 238 ). note: twbr should be 10 or higher if the twi operates in master mode. if twbr is lower than 10, the master may produce an incorrect output on sda and scl for the reminder of the byte. the prob- lem occurs when operating the twi in master mode, sending start + sla + r/w to a slave (a slave does not need to be connected to the bus for the condition to happen). 4.19.5.3 bus interface unit this unit contains the data and address shif t register (twdr), a start/stop controller and arbitration detection hardware. the twdr contains the address or data bytes to be transmitted, or the address or data bytes received. in addition to the 8-bit twdr, the bus interface unit also contains a register containing the (n)ack bit to be transmitted or received. this (n)ack regis- ter is not directly accessible by the application software. however, when re ceiving, it can be set or cleared by manipulating the twi control r egister (twcr). when in transmitter mode, the value of the received (n)ack bit can be determined by the value in the twsr. the start/stop controller is responsible for gene ration and detection of start, repeated start, and stop conditions. the start/stop controller is able to detect start and stop conditions even when the avr mcu is in one of the sleep modes, enabling the mcu to wake up if addressed by a master. if the twi has initiated a transmission as master, the arbitration detection hardware continu- ously monitors the transmission trying to determine if arbitration is in process. if the twi has lost an arbitration, the control unit is informed. correct action can then be taken and appropriate status codes generated. 4.19.5.4 address match unit the address match unit checks if received address bytes match the seven-bit address in the twi address register (twar). if the twi general call recognition enable (twgce) bit in the twar is written to one, all incoming address bits will also be compared against the general call address. upon an address match, the control unit is informed, allowing correct action to be taken. the twi may or may not acknowledge it s address, depending on settings in the twcr. the address match unit is able to compare addresses even when the avr mcu is in sleep mode, enabling the mcu to wake up if addressed by a master. if another interrupt (e.g., int0) occurs during twi power-down address match and wakes up the cpu, the twi aborts opera- tion and return to it?s idle state. if this cause any problems, ensure that twi address match is the only enabled interrupt when entering power-down. scl frequency cpu clock frequency 16 2(twbr) prescalervalue () ? + -------------------------------------------------------------------------------------------- = 236 4921e?auto?09/09 ata6602/ata6603 4.19.5.5 control unit the control unit monitors the twi bus and generates responses corresponding to settings in the twi control register (twcr). when an event requiring the attention of the application occurs on the twi bus, the twi interrupt flag (twint) is asserted. in the next clock cycle, the twi sta- tus register (twsr) is updated with a stat us code identifying the event. the twsr only contains relevant status information when the tw i interrupt flag is asserted. at all other times, the twsr contains a special stat us code indicating that no relevant status information is avail- able. as long as the twint flag is set, the scl line is held low. this allows the application software to complete its tasks before allowing the twi transmission to continue. the twint flag is set in the following situations: ? after the twi has transmitted a start/repeated start condition. ? after the twi has transmitted sla+r/w. ? after the twi has transmitted an address byte. ? after the twi has lost arbitration. ? after the twi has been addressed by own slave address or general call. ? after the twi has received a data byte. ? after a stop or repeated start has been received while still addressed as a slave. ? when a bus error has occurred due to an illegal start or stop condition. 4.19.6 twi register description 4.19.6.1 twi bit rate register ? twbr ? bits 7..0 ? twi bit rate register twbr selects the division factor for the bit rate generator. the bit rate generator is a fre- quency divider which generates the scl clock frequency in the master modes. see ?bit rate generator unit? on page 235 for calculating bit rates. 4.19.6.2 twi control register ? twcr the twcr is used to control the operation of the twi. it is used to enable the twi, to initiate a master access by applying a start condition to the bus, to generate a receiver acknowledge, to generate a stop condition, and to control halting of the bus while the data to be written to the bus are written to the twdr. it also indicates a write collision if data is attempted written to twdr while the regist er is inaccessible. ? bit 7 ? twint: twi interrupt flag this bit is set by hardware when the twi has finished its current job and expects application software response. if the i-bit in sreg and twie in tw cr are set, the mcu will jump to the twi interrupt vector. bit 76543210 twbr7 twbr6 twbr5 twbr4 twbr3 twbr2 twbr1 twbr0 twbr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 bit 76543210 twint twea twsta twsto twwc twen ? twie twcr read/write r/w r/w r/w r/w r r/w r r/w initial value00000000 237 4921e?auto?09/09 ata6602/ata6603 while the twint flag is set, the scl low period is stretched. the twint flag must be cleared by software by writing a logic one to it. note that this flag is not automatically cleared by hardware when executing the interrupt routine. also note that clearing this flag starts the operation of the twi, so all accesses to the twi address register (twar), twi status register (twsr), and twi data register (twdr) must be complete before clearing this flag. ? bit 6 ? twea: twi enable acknowledge bit the twea bit controls the generation of the acknowledge pulse. if the twea bit is written to one, the ack pulse is generated on the twi bus if the following conditions are met: the device?s own slave addre ss has been received. a general call has been received, while the twgce bit in the twar is set. a data byte has been received in master receiver or slave receiver mode. by writing the twea bit to zero, the device can be virtually disconnected from the 2-wire serial bus temporarily. address recognition can then be resumed by writing the twea bit to one again. ? bit 5 ? twsta: twi start condition bit the application writes the twsta bit to one when it desires to become a master on the 2-wire serial bus. the twi hard ware checks if the bus is available, and generates a start condition on the bus if it is free. however, if the bus is not free, the twi waits until a stop condition is detected, and then generates a new start condition to claim the bus master status. twsta must be cleared by software when the start condition has been transmitted. ? bit 4 ? twsto: twi stop condition bit writing the twsto bit to one in master mode will generate a stop condition on the 2-wire serial bus. when the stop condition is executed on the bus, the twsto bit is cleared automatically. in slave mode, setting the twsto bit can be used to recover from an error condition. this will not generate a stop condi tion, but the twi returns to a well-defined unaddressed slave mode and releases the sc l and sda lines to a high impedance state. ? bit 3 ? twwc: twi write collision flag the twwc bit is set when attempting to write to the twi data register ? twdr when twint is low. this flag is cleared by writ ing the twdr register when twint is high. ? bit 2 ? twen: twi enable bit the twen bit enables twi operation and activates the twi interface. when twen is writ- ten to one, the twi takes control over the i/o pins connected to the scl and sda pins, enabling the slew-rate limiters and spike filters. if this bit is written to zero, the twi is switched off and all twi transmissions are terminated, regardless of any ongoing operation. ? bit 1 ? res: reserved bit this bit is a reserved bit an d will always read as zero. ? bit 0 ? twie: twi interrupt enable when this bit is written to on e, and the i-bit in sreg is se t, the twi interrupt request will be activated for as long as the twint flag is high. 238 4921e?auto?09/09 ata6602/ata6603 4.19.6.3 twi status register ? twsr ? bits 7..3 ? tws: twi status these 5 bits reflect the status of the twi logic and the 2-wire serial bus. the different status codes are described later in this section. note that the value read from twsr contains both the 5-bit status value and the 2-bit prescale r value. the application designer should mask the prescaler bits to zero when checking the status bits. this makes status checking inde- pendent of prescaler setting. this approach is used in this datasheet, unless otherwise noted. ? bit 2 ? res: reserved bit this bit is reserved and will always read as zero. ? bits 1..0 ? twps: twi prescaler bits these bits can be read and written, and control the bit rate prescaler. to calculate bit rates, see ?bit rate generator unit? on page 235 . the value of twps1..0 is used in the equation. 4.19.6.4 twi data register ? twdr in transmit mode, twdr contains the next byte to be transmitted. in receive mode, the twdr contains the last byte received. it is writable while the twi is not in the process of shifting a byte. this occurs when the twi interrupt flag (twint) is set by hardware. note that the data regis- ter cannot be initialized by the user before the first interrupt occurs. the data in twdr remains stable as long as twint is se t. while data is shifted out, data on the bus is simultaneously shifted in. twdr always contains the last byte present on the bus, except after a wake up from a sleep mode by the twi interrupt. in this case, the contents of twdr is undefined. in the case of a lost bus arbitration, no data is lost in the transition from master to slave. handling of the ack bit is controlled automatically by the twi logic, the cpu cannot access the ack bit directly. ? bits 7..0 ? twd: twi data register these eight bits constitute the next data byte to be transmitted, or the latest data byte received on the 2-wire serial bus. bit 76543210 tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 twsr read/write r r r r r r r/w r/w initial value11111000 table 4-88. twi bit rate prescaler twps1 twps0 prescaler value 001 014 1016 1164 bit 76543210 twd7 twd6 twd5 twd4 twd3 twd2 twd1 twd0 twdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111111 239 4921e?auto?09/09 ata6602/ata6603 4.19.6.5 twi (slave) address register ? twar the twar should be loaded with the 7-bit slave address (in the seven most significant bits of twar) to which the twi will respond when programmed as a slave transmitter or receiver, and not needed in the master modes. in multi master systems, twar must be set in masters which can be addressed as slaves by other masters. the lsb of twar is used to enable recognition of the general call address (0x00). there is an associated address comparator that looks for the slave address (or general call address if enabled) in the received serial address. if a match is found, an interrupt request is generated. ? bits 7..1 ? twa: twi (slave) address register these seven bits constitute the slave address of the twi unit. ? bit 0 ? twgce: twi general call recognition enable bit if set, this bit enables the recognition of a general call given over the 2-wire serial bus. 4.19.6.6 twi (slave) address mask register ? twamr ? bits 7..1 ? twam: twi address mask the twamr can be loaded with a 7-bit salve address mask. each of the bits in twamr can mask (disable) the corresponding address bi ts in the twi address register (twar). if the mask bit is set to one then the address match logic ignores the compare between the incoming address bit and the corresponding bit in twar. figure 4-86 shown the address match logic in detail. figure 4-86. twi address match logic, block diagram ? bit 0 ? res: reserved bit this bit is an unused bit in the ata660 2/ata6603, and will always read as zero. bit 76543210 twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce twar read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value11111110 bit 76543210 twam[6:0] ? twamr read/write r/w r/w r/w r/w r/w r/w r/w r initial value00000000 addres s match address bit comparator 0 address bit comparator 6..1 twar0 twamr0 address bit 0 240 4921e?auto?09/09 ata6602/ata6603 4.19.7 using the twi the avr twi is byte-oriented and interrupt based. interrupts are issued after all bus events, like reception of a byte or transmission of a start condition. because the twi is interrupt-based, the application software is free to carry on other operations during a twi byte transfer. note that the twi interrupt enable (twie) bit in twcr to gether with the global interrupt enable bit in sreg allow the application to decide whether or not assertion of the twint flag should gener- ate an interrupt request. if the twie bit is clear ed, the application must poll the twint flag in order to detect actions on the twi bus. when the twint flag is asserted, the twi has finished an operation and awaits application response. in this case, the twi status register (twsr) contains a value indicating the current state of the twi bus. the application software can then decide how the twi should behave in the next twi bus cycle by manipulating the twcr and twdr registers. figure 4-87 is a simple example of how the application can interface to the twi hardware. in this example, a master wishes to transmit a single data byte to a slave. this description is quite abstract, a more detailed explanation follows later in this section. a simple code example imple- menting the desired behavior is also presented. figure 4-87. interfacing the application to the twi in a typical transmission 1. the first step in a twi transmission is to transmit a start condition. this is done by writing a specific value into twcr, instructing the twi hardware to transmit a start condition. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the tw int bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmission of the start condition. 2. when the start condition has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the start condition has success- fully been sent. start sla+w a data a stop 1. application writes to twcr to initiate transmission of start 2. twint set. status code indicates start condition sent 4. twint set. status code indicates sla+w sent, ack received 6. twint set. status code indicates data sent, ack received 3. check twsr to see if start was sent. application loads sla+w into twdr, and loads appropriate control signals into twcr, makin sure that twint is written to one, and twsta is written to zero. 5. check twsr to see if sla+w was sent and ack received. application loads data into twdr, and loads appropriate control signals into twcr, making sure that twint is written to one 7. check twsr to see if data was sent and ack received. application loads appropriate control signals to send stop into twcr, making sure that twint is written to one twi bus indicates twint set application action twi hardware action 241 4921e?auto?09/09 ata6602/ata6603 3. the application software should now examine the value of twsr, to make sure that the start condition was successfully transmitted. if twsr indicates otherwise, the appli- cation software might take some special acti on, like calling an error routine. assuming that the status code is as expected, the application must load sla+w into twdr. remember that twdr is used both for address and data. after twdr has been loaded with the desired sla+w, a specific value must be written to twcr, instructing the twi hardware to transmit the sla+w present in twdr. which value to write is described later on. however, it is important t hat the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the application has cleared twint, the twi will initiate transmis sion of the address packet. 4. when the address packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the address packet has success- fully been sent. the status code will also reflect whether a slave acknowledged the packet or not. 5. the application software should now examine the value of twsr, to make sure that the address packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some spe- cial action, like calling an error routine. assu ming that the status code is as expected, the application must load a data packet into twdr. subsequently, a specific value must be written to twcr, instructing the twi hardware to transmit the data packet present in twdr. which value to write is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immedi- ately after the application has cleared twin t, the twi will initiate transmission of the data packet. 6. when the data packet has been transmitted, the twint flag in twcr is set, and twsr is updated with a status code indicating that the data packet has successfully been sent. the status code will also reflec t whether a slave acknowledged the packet or not. 7. the application software should now examine the value of twsr, to make sure that the data packet was successfully transmitted, and that the value of the ack bit was as expected. if twsr indicates otherwise, the application software might take some spe- cial action, like calling an error routine. assu ming that the status code is as expected, the application must write a specific valu e to twcr, instructing the twi hardware to transmit a stop condition. which value to wr ite is described later on. however, it is important that the twint bit is set in the value written. writing a one to twint clears the flag. the twi will not start any operation as long as the twint bit in twcr is set. immediately after the applicat ion has cleared twint, the twi will initiate transmission of the stop condition. note that twint is not set after a stop condition has been sent. 242 4921e?auto?09/09 ata6602/ata6603 even though this example is simple, it shows t he principles involved in all twi transmissions. these can be summarized as follows: ? when the twi has finished an operation and expects application response, the twint flag is set. the scl line is pull ed low until twint is cleared. ? when the twint flag is set, the user must update all twi registers with the value relevant for the next twi bus cycle. as an example, twdr must be loaded with the value to be transmitted in the next bus cycle. ? after all twi register updates and other pending application software tasks have been completed, twcr is written. when writing tw cr, the twint bit should be set. writing a one to twint clears the flag. the twi will then commence executing whatever operation was specified by the twcr setting. in the following an assembly and c implementation of the example is given. note that the code below assumes that several definitions have been made, for example by using include-files. 243 4921e?auto?09/09 ata6602/ata6603 table 4-89. assembly code example c example comments 1 ldi r16, (1< 245 4921e?auto?09/09 ata6602/ata6603 figure 4-88. data transfer in master transmitter mode a start condition is sent by wr iting the following value to twcr: twen must be set to enable the 2-wire serial interface, twsta must be written to one to trans- mit a start condition and twint must be written to one to cl ear the twint flag. the twi will then test the 2-wire serial bus and generate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hardware, and the status code in twsr will be 0x08 (see table 4-90 on page 246 ). in order to enter mt mode, sla+w must be transmitted. this is done by writing sla+w to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to twcr: when sla+w have been transmitted and an acknowledgement bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x18, 0x20, or 0x38. the appropriate action to be taken for each of these status codes is detailed in table 4-90 on page 246 . when sla+w has been successfully transmitted, a data packet should be transmitted. this is done by writing the data byte to twdr. twdr must only be written when twint is high. if not, the access will be discarded, and the write collision bit (twwc) will be set in the twcr regis- ter. after updating twdr, the twint bit should be cleared (by writing it to one) to continue the transfer. this is acco mplished by writing the following value to twcr: this scheme is repeated until the last byte has been sent and the transfer is ended by generat- ing a stop condition or a repeated start condition. a stop condition is generated by writing the following value to twcr: device 1 master transmitter device 2 slave receiver device 3 device n sda scl ........ r1 r2 v cc twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x 246 4921e?auto?09/09 ata6602/ata6603 a repeated start condition is generated by writing the following value to twcr: after a repeated start condition (state 0x10) th e 2-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode with- out losing control of the bus. twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x table 4-90. status codes for master transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+w 0 0 1 x sla+w will be transmitted; ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+w or load sla+r 0 0 0 0 1 1 x x sla+w will be transmitted; ack or not ack will be received sla+r will be transmitted; logic will switch to master receiver mode 0x18 sla+w has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x20 sla+w has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x28 data byte has been transmitted; ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x30 data byte has been transmitted; not ack has been received load data byte or no twdr action or no twdr action or no twdr action 0 1 0 1 0 0 1 1 1 1 1 1 x x x x data byte will be transmitted and ack or not ack will be received repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x38 arbitration lost in sla+w or data bytes no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode entered a start condition will be transmitted when the bus becomes free 247 4921e?auto?09/09 ata6602/ata6603 figure 4-89. formats and states in the master transmitter mode 4.19.8.2 master receiver mode in the master receiver mode, a number of data bytes are received from a slave transmitter (slave see figure 4-90 on page 248 ). in order to enter a master mode, a start condition must be transmitted. the format of the following address packet determines whether master transmit- ter or master receiver mode is to be entered. if sla+w is transmitted, mt mode is entered, if sla+r is transmitted, mr mode is entered. all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. s sla w a data a p $08 $18 $28 r sla w $10 ap $20 p $30 a or a $38 a other master continues a or a $38 other master continues r a $68 other master continues $78 $b0 to corresponding states in slave mode mt mr successfull transmission to a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address not acknowledge received after a data byte arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the prescaler bits are zero or masked to zero s 248 4921e?auto?09/09 ata6602/ata6603 figure 4-90. data transfer in mast er receiver mode a start condition is sent by wr iting the following value to twcr: twen must be written to one to enable the 2-wire serial interface, twsta must be written to one to transmit a start condition and twint must be set to clear the twint flag. the twi will then test the 2-wire serial bus and generate a start condition as soon as the bus becomes free. after a start condition has been transmitted, the twint flag is set by hard- ware, and the status code in twsr will be 0x08 (see table 4-90 on page 246 ). in order to enter mr mode, sla+r must be transmitted. this is done by writing sla+r to twdr. thereafter the twint bit should be cleared (by writing it to one) to continue the transfer. this is accomplished by writing the following value to twcr: when sla+r have been transmitted and an acknowledgement bit has been received, twint is set again and a number of status codes in twsr are possible. possible status codes in master mode are 0x38, 0x40, or 0x48. the appropriate action to be taken for each of these status codes is detailed in table 4-91 on page 249 . received data can be read from the twdr register when the twint flag is set high by hardware. this scheme is repeated until the last byte has been received. after the last byte has been received, the mr should inform the st by sending a nack after the last received data byte. the transfer is ended by generating a stop condition or a repeated start condition. a stop condition is generated by writing the following value to twcr: a repeated start condition is generated by writing the following value to twcr: twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x00 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x01 x1 0 x twcr twint twea twsta twsto twwc twen ? twie value 1 x10 x1 0 x device 1 master receiver device 2 slave transmitter device 3 device n sda scl ........ r1 r2 v cc 249 4921e?auto?09/09 ata6602/ata6603 after a repeated start condition (state 0x10) th e 2-wire serial interface can access the same slave again, or a new slave without transmitting a stop condition. repeated start enables the master to switch between slaves, master transmitter mode and master receiver mode with- out losing control over the bus. table 4-91. status codes for master receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x08 a start condition has been transmitted load sla+r 0 0 1 x sla+r will be transmitted ack or not ack will be received 0x10 a repeated start condition has been transmitted load sla+r or load sla+w 0 0 0 0 1 1 x x sla+r will be transmitted ack or not ack will be received sla+w will be transmitted logic will switch to master transmitter mode 0x38 arbitration lost in sla+r or not ack bit no twdr action or no twdr action 0 1 0 0 1 1 x x 2-wire serial bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free 0x40 sla+r has been transmitted; ack has been received no twdr action or no twdr action 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x48 sla+r has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 0x50 data byte has been received; ack has been returned read data byte or read data byte 0 0 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x58 data byte has been received; not ack has been returned read data byte or read data byte or read data byte 1 0 1 0 1 1 1 1 1 x x x repeated start will be transmitted stop condition will be transmitted and twsto flag will be reset stop condition followed by a start condition will be transmitted and twsto flag will be reset 250 4921e?auto?09/09 ata6602/ata6603 figure 4-91. formats and states in the master receiver mode 4.19.8.3 slave receiver mode in the slave receiver mode, a number of data bytes are received from a master transmitter (see figure 4-92 ). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 4-92. data transfer in slave receiver mode s sla r a data a $08 $40 $50 sla r $10 ap $48 a or a $38 other master continues $38 other master continues w a $68 other master continues $78 $b0 to corresponding states in slave mode mr mt successfull reception from a slave receiver next transfer started with a repeated start condition not acknowledge received after the slave address arbitration lost in slave address or data byte arbitration lost and addressed as slave data a n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the prescaler bits are zero or masked to zero p data a $58 a r s device 3 device n sda scl ........ r1 r2 v cc device 2 master transmitter device 1 slave receiver 251 4921e?auto?09/09 ata6602/ata6603 to initiate the slave receiver mode, twar and twcr must be initialized as follows: the upper 7 bits are the address to which the 2-wire serial interface will respond when addressed by a master. if the lsb is set, the twi will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgement of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?0? (write), the twi will operate in sr mode, otherwise st mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status c ode is used to determine the appropriate soft- ware action. the appropriate action to be taken for each status code is detailed in table 4-92 on page 252 . the slave receiver mode may also be entere d if arbitration is lo st while the twi is in the master mode (see states 0x68 and 0x78). if the twea bit is reset during a transfer, the tw i will return a ?not acknowledge? (?1?) to sda after the next received data byte. this can be used to indicate that the slave is not able to receive any more bytes. while twea is zero, the twi does not acknowledge its own slave address. however, the 2-wire se rial bus is still monitored and address recognit ion may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the 2-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its own slave ad dress or the general call address by using the 2-wire serial bus clock as a clock sour ce. the part will then wake up from sleep and the twi will hold the scl clock low during the wake up and until the twin t flag is cleared (by writing it to one). further data reception will be carried out as normal, with the avr clocks run- ning as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. note that the 2-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 252 4921e?auto?09/09 ata6602/ata6603 table 4-92. status codes for slave receiver mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0x60 own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x68 arbitration lost in sla+r/w as master; own sla+w has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x70 general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x78 arbitration lost in sla+r/w as master; general call address has been received; ack has been returned no twdr action or no twdr action x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x80 previously addressed with own sla+w; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x88 previously addressed with own sla+w; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 253 4921e?auto?09/09 ata6602/ata6603 0x90 previously addressed with general call; data has been received; ack has been returned read data byte or read data byte x x 0 0 1 1 0 1 data byte will be received and not ack will be returned data byte will be received and ack will be returned 0x98 previously addressed with general call; data has been received; not ack has been returned read data byte or read data byte or read data byte or read data byte 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xa0 a stop condition or repeated start condition has been received while still addressed as slave no action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free table 4-92. status codes for slave receiver mode (continued) status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 254 4921e?auto?09/09 ata6602/ata6603 figure 4-93. formats and states in the slave receiver mode 4.19.8.4 slave transmitter mode in the slave transmitter mode, a number of data bytes are transmitted to a master receiver (see figure 4-94 ). all the status codes mentioned in this section assume that the prescaler bits are zero or are masked to zero. figure 4-94. data transfer in slave transmitter mode s sla w a data a $60 $80 $88 a $68 reception of the own slave address and one or more data bytes. all are acknowledged last data byte received is not acknowledged arbitration lost as master and addressed as slave reception of the general call address and one or more data bytes last data byte received is not acknowledged n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the prescaler bits are zero or masked to zero p or s data a $80 $a0 p or s a a data a $70 $90 $98 a $78 p or s data a $90 $a0 p or s a general call arbitration lost as master and addressed as slave by general call data a device 3 device n sda scl ........ r1 r2 v cc device 2 master receiver device 1 slave transmitter 255 4921e?auto?09/09 ata6602/ata6603 to initiate the slave transmitter mode, twar and twcr must be in itialized as follows: the upper seven bits are the address to which the 2-wire serial interface will respond when addressed by a master. if the lsb is set, the twi will respond to the general call address (0x00), otherwise it will ignore the general call address. twen must be written to one to enable the twi. the twea bit must be written to one to enable the acknowledgement of the device?s own slave address or the general call address. twsta and twsto must be written to zero. when twar and twcr have been initialized, the twi waits until it is addressed by its own slave address (or the general call address if enabled) followed by the data direction bit. if the direction bit is ?1? (read), the twi will operate in st mode, otherw ise sr mode is entered. after its own slave address and the write bit have been received, the twint flag is set and a valid status code can be read from twsr. the status c ode is used to determine the appropriate soft- ware action. the appropriate action to be taken for each status code is detailed in table 4-93 on page 256 . the slave transmitter mode may also be entered if arbitration is lost while the twi is in the master mode (see state 0xb0). if the twea bit is written to zero during a transfer, the twi will transm it the last byte of the trans- fer. state 0xc0 or state 0xc8 will be entere d, depending on whether the master receiver transmits a nack or ack after the final byte. the twi is switched to the not addressed slave mode, and will ignore the mast er if it continues th e transfer. thus the ma ster receiver receives all ?1? as serial data. state 0xc8 is entered if the master demands additional data bytes (by transmitting ack), even though the slave has transmitted the last byte (twea zero and expect- ing nack from the master). while twea is zero, the twi does not respond to its own slave address. however, the 2-wire serial bus is still monitored an d address recognition may resume at any time by setting twea. this implies that the twea bit may be used to temporarily isolate the twi from the 2-wire serial bus. in all sleep modes other than idle mode, the clock system to the twi is turned off. if the twea bit is set, the interface can still acknowledge its own slave ad dress or the general call address by using the 2-wire serial bus clock as a clock sour ce. the part will then wake up from sleep and the twi will hold the scl clock will low during th e wake up and until the twint flag is cleared (by writing it to one). further data tr ansmission will be carried out as normal, with the avr clocks running as normal. observe that if the avr is set up with a long start-up time, the scl line may be held low for a long time, blocking other data transmissions. note that the 2-wire serial interface data register ? twdr does not reflect the last byte present on the bus when waking up from these sleep modes. twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce value device?s own slave address twcr twint twea twsta twsto twwc twen ? twie value 0 100 01 0 x 256 4921e?auto?09/09 ata6602/ata6603 table 4-93. status codes for slave transmitter mode status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xa8 own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xb0 arbitration lost in sla+r/w as master; own sla+r has been received; ack has been returned load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xb8 data byte in twdr has been transmitted; ack has been received load data byte or load data byte x x 0 0 1 1 0 1 last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received 0xc0 data byte in twdr has been transmitted; not ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 0xc8 last data byte in twdr has been transmitted (twea = ?0?); ack has been received no twdr action or no twdr action or no twdr action or no twdr action 0 0 1 1 0 0 0 0 1 1 1 1 0 1 0 1 switched to the not addressed slave mode; no recognition of own sla or gca switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1? switched to the not addressed slave mode; no recognition of own sla or gca; a start condition will be transmitted when the bus becomes free switched to the not addressed slave mode; own sla will be recognized; gca will be recognized if twgce = ?1?; a start condition will be transmitted when the bus becomes free 257 4921e?auto?09/09 ata6602/ata6603 figure 4-95. formats and states in the slave transmitter mode 4.19.8.5 miscellaneous states there are two status codes that do not correspond to a defined twi state (see table 4-94 ). status 0xf8 indicates that no relevant inform ation is available because the twint flag is not set. this occurs between other states, and when the twi is not involved in a serial transfer. status 0x00 indicates that a bus error has occu rred during a 2-wire serial bus transfer. a bus error occurs when a start or stop condition occurs at an illegal position in the format frame. examples of such illegal positions are during the serial transfer of an address byte, a data byte, or an acknowledge bit. when a bus error occurs, twint is set. to recover from a bus error, the twsto flag must set and twint must be cleared by writing a logic one to it. this causes the twi to enter the not addressed slave mode and to clear the twsto flag (no other bits in twcr are affected). the sda and scl lines are released, and no stop condition is transmitted. s sla r a data a $a8 $b8 a $b0 reception of the own slave address and one or more data bytes last data byte transmitted. switched to not addressed slave (twea = '0') arbitration lost as master and addressed as slave n from master to slave from slave to master any number of data bytes and their associated acknowledge bits this number (contained in twsr) corresponds to a defined state of the 2-wire serial bus. the prescaler bits are zero or masked to zero p or s data $c0 data a a $c8 p or s all 1's a table 4-94. miscellaneous states status code (twsr) prescaler bits are 0 status of the 2-wire serial bus and 2-wire serial interface hardware application software response next action taken by twi hardware to/from twdr to twcr sta sto twint twea 0xf8 no relevant state information available; twint = ?0? no twdr action no twcr action wa it or proceed current transfer 0x00 bus error due to an illegal start or stop condition no twdr action 0 1 1 x only the internal hardware is affected, no stop condition is sent on the bus. in all cases, the bus is released and twsto is cleared. 258 4921e?auto?09/09 ata6602/ata6603 4.19.8.6 combining several twi modes in some cases, several twi modes must be combined in order to complete the desired action. consider for example reading data from a serial eeprom. typically, such a transfer involves the following steps: 1. the transfer must be initiated. 2. the eeprom must be instructed what location should be read. 3. the reading must be performed. 4. the transfer must be finished. note that data is transmitted both from master to slave and vice versa. the master must instruct the slave what location it wants to read, r equiring the use of the mt mode. subsequently, data must be read from the slave, implying the use of the mr mode. thus, the transfer direction must be changed. the master must keep control of the bus during all these steps, and the steps should be carried out as an atomical operation. if this principle is violated in a multi master sys- tem, another master can alter the data pointer in the eeprom between steps 2 and 3, and the master will read the wrong data lo cation. such a change in transfe r direction is accomplished by transmitting a repeated start between the trans mission of the address byte and reception of the data. after a repeated start, the master keeps ownership of the bus. the following figure shows the flow in this transfer. figure 4-96. combining several twi modes to access a serial eeprom 4.19.9 multi-master systems and arbitration if multiple masters are connected to the same bus, transmissions may be initiated simultane- ously by one or more of them. the twi standar d ensures that such situations are handled in such a way that one of the mast ers will be allowed to proceed wit h the transfer, and that no data will be lost in the process. an example of an ar bitration situation is depicted below, where two masters are trying to transmit data to a slave receiver. master transmitter master receiver s = start rs = repeated start p = stop transmitted from master to slave transmitted from slave to master s sla+w a address a rs sla+r a data a p 259 4921e?auto?09/09 ata6602/ata6603 figure 4-97. an arbitration example several different scenarios may arise during arbitration, as described below: ? two or more masters are performing identical communication with the same slave. in this case, neither the slave nor any of the masters will know about the bus contention. ? two or more masters are accessing the same slave with different data or direction bit. in this case, arbitration will occur, either in the read /write bit or in the data bits. the masters trying to output a one on sda while another master outputs a zero will lose the arbitration. losing masters will switch to not addressed slave mode or wa it until the bus is free and transmit a new start condition, depending on application software action. ? two or more masters are access ing different slaves. in this ca se, arbitration will occur in the sla bits. masters trying to ou tput a one on sda while another mast er outputs a zero will lose the arbitration. masters losing arbitration in sla will switch to slave mode to check if they are being addressed by the winning master. if addressed, they will switch to sr or st mode, depending on the value of the read/write bit. if they are not being addressed, they will switch to not addressed slave mode or wait until the bus is free and transmit a new start condition, depending on application software action. this is summarized in figure 4-98 . possible status values are given in circles. figure 4-98. possible status codes caused by arbitration device 1 master transmitter device n sda scl ........ r1 r2 v cc device 2 master transmitter device 3 slave receiver own address / general call received arbitration lost in sla twi bus will be released and not addressed slave mode will be entered a start condition will be transmitted when the bus becomes free no arbitration lost in data direction ye s write data byte will be received and not ack will be returned data byte will be received and ack will be returned last data byte will be transmitted and not ack should be received data byte will be transmitted and ack should be received read b0 68/78 38 sla start data stop 260 4921e?auto?09/09 ata6602/ata6603 4.20 analog comparator the analog comparator compares the input values on the positive pin ain0 and negative pin ain1. when the voltage on the positive pin ain0 is higher than the voltage on the negative pin ain1, the analog comparator output, aco, is set. the comparator?s output can be set to trigger the timer/counter1 input capture function. in addition, the comparator can trigger a separate interrupt, exclusive to the analog comparator. th e user can select interrupt triggering on com- parator output rise, fall or toggle. a block diagram of the comparator and its surrounding logic is shown in figure 4-99 . the power reduction adc bit, pradc, in ?power reduction register - prr? on page 64 must be disabled by writing a logical zero to be able to use the adc input mux. figure 4-99. analog comparator block diagram (2) notes: 1. see table 4-96 on page 262 . 2. refer to table 4-38 on page 102 for analog comparator pin placement. 4.20.1 adc control and status register b ? adcsrb ? bit 6 ? acme: analog comparator multiplexer enable when this bit is written logic one and the a dc is switched off (ade n in adcsra is zero), the adc multiplexer selects th e negative input to the analog comparator. when this bit is written logic zero, ain1 is applied to the negative input of the analog comparator. for a detailed description of this bit (see ?analog comparator multiplexed input? on page 262 ). acbg bandgap reference adc multiplexer output acme aden (1) ain0 ain1 acd vcc interrupt select acie acis1 acis0 acic aco to t/c1 capture trigger mux analog comparator irq aci bit 7 6543210 ?acme ? ? ? adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value0 0000000 261 4921e?auto?09/09 ata6602/ata6603 4.20.2 analog comparator control and status register ? acsr ? bit 7 ? acd: analog comparator disable when this bit is written logic one, the power to the analog comparator is switched off. this bit can be set at any time to turn off th e analog comparator. this will reduce power con- sumption in active and idle mode. when changing the acd bit, the analog comparator interrupt must be disabled by clearing the acie bit in acsr. otherwise an interrupt can occur when the bit is changed. ? bit 6 ? acbg: analog comparator bandgap select when this bit is set, a fixed bandgap reference voltage replaces the positive input to the analog comparator. when this bit is cleared, ain0 is applied to the positive input of the ana- log comparator (see ?internal voltage reference? on page 71 ). ? bit 5 ? aco: analog comparator output the output of the analog comparator is synchronized and then directly connected to aco. the synchronization introduces a delay of 1 - 2 clock cycles. ? bit 4 ? aci: analog comparator interrupt flag this bit is set by hardware when a comparator output event triggers the interrupt mode defined by acis1 and acis0. the analog comparator interrupt routine is executed if the acie bit is set and the i-bit in sreg is set. aci is cleared by hardware when executing the corresponding interrupt handling vector. alternatively, aci is cleared by writing a logic one to the flag. ? bit 3 ? acie: analog comparator interrupt enable when the acie bit is written logic one and the i-bit in the status register is set, the analog comparator interrupt is activated. when written logic zero, the interrupt is disabled. ? bit 2 ? acic: analog comparator input capture enable when written logic one, this bit enables the input capture function in timer/counter1 to be triggered by the analog comparator. the comparator output is in this case directly con- nected to the input capture fr ont-end logic, making the com parator utilize t he noise canceler and edge select features of the timer/counter1 input capture interrupt. when written logic zero, no connection between the analog comparat or and the input capture function exists. to make the comparator trigger the timer/counter1 input capture interrupt, the icie1 bit in the timer interrupt mask register (timsk1) must be set. ? bits 1, 0 ? acis1, acis0: analog comparator interrupt mode select these bits determine which comparator events that trigger the analog comparator interrupt. the different settings are shown in table 4-95 on page 262 . bit 76543210 acd acbg aco aci acie acic acis1 acis0 acsr read/write r/w r/w r r/w r/w r/w r/w r/w initial value00n/a00000 262 4921e?auto?09/09 ata6602/ata6603 when changing the acis1/acis0 bits, the analog comparator interrupt must be disabled by clearing its interrupt enable bit in the acsr register. otherwise an interrupt can occur when the bits are changed. 4.20.3 analog comparator multiplexed input it is possible to select any of the adc7..0 pins to replace the negative input to the analog com- parator. the adc multiplexer is used to select this input, and consequently, the adc must be switched off to utilize this feature. if the analog comparator multiplexer enable bit (acme in adcsrb) is set and the adc is switched off (a den in adcsra is zero), mux2..0 in admux select the input pin to replace the negative input to the analog comparator, as shown in table 4-96 . if acme is cleared or aden is set, ain1 is applied to the negative input to the analog comparator. 4.20.3.1 digital input disable register 1 ? didr1 ? bit 7..2 ? res: reserved bits these bits are unused bits in the ata6 602/ata6603, and will a lways read as zero. ? bit 1, 0 ? ain1d, ain0d: ai n1, ain0 digital input disable when this bit is written logic one, the digital input buffer on the ain1/0 pin is disabled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the ain1/0 pin and the digita l input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. table 4-95. acis1/acis0 settings acis1 acis0 interrupt mode 0 0 comparator interrupt on output toggle. 01reserved 1 0 comparator interrupt on falling output edge. 1 1 comparator interrupt on rising output edge. table 4-96. analog comparator multiplexed input acme aden mux2..0 analog co mparator negative input 0 x xxx ain1 1 1 xxx ain1 10 000adc0 10 001adc1 10 010adc2 10 011adc3 10 100adc4 10 101adc5 10 110adc6 10 111adc7 bit 76543210 ??????ain1dain0ddidr1 read/writerrrrrrr/wr/w initial value00000000 263 4921e?auto?09/09 ata6602/ata6603 4.21 analog-to-digital converter 4.21.1 features ? 10-bit resolution ? 0.5 lsb integral non-linearity ? 2 lsb absolute accuracy ? 13 - 260 s conversion time ? up to 15 ksps at maximum resolution ? 6 multiplexed single ended input channels ? 2 additional multiplexed single ended input channels (tqfp and qfn package only) ? optional left adjustment for adc result readout ? 0 - v cc adc input voltage range ? selectable 1.1v adc reference voltage ? free running or single conversion mode ? interrupt on adc conversion complete ? sleep mode no ise canceler the ata6602/ata6603 features a 10-bit successive approximation adc. the adc is con- nected to an 8-channel analog multiplexer which allows eigh t single-ended voltage inputs constructed from the pins of port a. the single-ended voltage inputs refer to 0v (gnd). the adc contains a sample and hold circuit whic h ensures that the input voltage to the adc is held at a constant level during conversion. a block diagram of the adc is shown in figure 4-100 on page 264 . the adc has a separate analog supply voltage pin, av cc . av cc must not differ more than 0.3v from v cc . see the paragraph ?adc noise canceler? on page 270 on how to connect this pin. internal reference voltages of nominally 1.1v or av cc are provided on-chip. the voltage refer- ence may be externally decoupled at the aref pi n by a capacitor for better noise performance. the power reduction adc bit, pradc, in ?power reduction register - prr? on page 64 must be disabled by writing a logical zero to enable the adc. 264 4921e?auto?09/09 ata6602/ata6603 figure 4-100. analog to digital converter block schematic operation the adc converts an analog input voltage to a 10-bit digital value through successive approxi- mation. the minimum value represents gnd and the maximum value represents the voltage on the aref pin minus 1 lsb. optionally, av cc or an internal 1.1v reference voltage may be con- nected to the aref pin by writing to the refsn bits in the admux register. the internal voltage reference may thus be decoupled by an external capacitor at the aref pin to improve noise immunity. the analog input channel is selected by writing to the mux bits in admux. any of the adc input pins, as well as gnd and a fixed bandgap voltage reference, can be selected as single ended inputs to the adc. the adc is enabled by sett ing the adc enable bit, aden in adcsra. volt- age reference and input channel se lections will not go into effect until aden is set. the adc does not consume power when aden is cleared, so it is recommended to switch off the adc before entering power saving sleep modes. adc conversion complete irq 8-bit data bus 15 0 adc multiplexer select (admux) adc ctrl. & status register (adcsra) adc data register (adch/adcl) mux2 adie adfr adsc aden adif adif mux1 mux0 adps0 adps1 adps2 mux3 conversion logic 10-bit dac + - sample and hold comparator internal 1.1v reference mux decoder avcc adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 refs0 refs1 adlar channel selection adc[9:0] adc multiplexer output aref bandgap reference prescaler gnd input mux 265 4921e?auto?09/09 ata6602/ata6603 the adc generates a 10-bit result which is pr esented in the adc data registers, adch and adcl. by default, the result is presented right adjusted, but can optionally be presented left adjusted by setting the adlar bit in admux. if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch, to ensure that the content of the data registers belongs to the same conversion. once adcl is read, adc access to data registers is blocked. this means that if adcl has been read, and a conversion completes before adch is read, neither register is updated and the result fr om the conversion is lost. when adch is read, adc access to the adch and ad cl registers is re-enabled. the adc has its own interrupt which can be triggered when a conversion completes. when adc access to the data registers is prohibited between reading of adch and adcl, the interrupt will trigger even if the result is lost. 4.21.2 starting a conversion a single conversion is started by disabli ng the power reduction adc bit, pradc, in ?power reduction register - prr? on page 64 by writing a logical zero to it and writing a logical one to the adc start conversion bit, adsc. this bit stays high as long as the conversion is in progress and will be cleared by hardwa re when the conversion is comple ted. if a different data channel is selected while a conversion is in progress, the adc will finish th e current conversion before per- forming the channel change. alternatively, a conversion can be triggered automatically by various sources. auto triggering is enabled by setting the adc auto trigger enable bi t, adate in adcsra. the trigger source is selected by setting the adc trig ger select bits, adts in adcsrb (see description of the adts bits for a list of the trigger sources). when a positive edge occurs on the selected trigger signal, the adc prescaler is reset and a conversion is st arted. this provides a method of starting con- versions at fixed intervals. if the trigger signal still is set when the conversion completes, a new conversion will not be star ted. if another positive edge occurs on the trigger si gnal during con- version, the edge will be ignored. note that an interrupt flag will be set even if the specific interrupt is disabled or the global interrupt enable bit in sreg is cleared. a conversion can thus be triggered without causing an interrupt. however, the interrupt flag must be cleared in order to trigger a new conversion at the next interrupt event. figure 4-101. adc auto trigger logic adsc adif source 1 source n adts[2:0] conversion logic prescaler start clk adc . . . . edge detector adate 266 4921e?auto?09/09 ata6602/ata6603 using the adc interrupt flag as a trigger source makes the adc start a new conversion as soon as the ongoing conversion has finished. the adc then operates in free running mode, con- stantly sampling and updating the adc data register. the first conversion must be started by writing a logical one to the adsc bit in adcs ra. in this mode the adc will perform successive conversions independently of whether the a dc interrupt flag, adif is cleared or not. if auto triggering is enabled, single conversi ons can be started by writing adsc in adcsra to one. adsc can also be used to determine if a conversion is in progress. the adsc bit will be read as one during a conversion, independently of how the conversion was started. 4.21.3 prescaling and conversion timing figure 4-102. adc prescaler by default, the successive approximation circuitry requires an input clock frequency between 50 khz and 200 khz to get maximum resolution. if a lower resolution than 10 bits is needed, the input clock frequency to the adc can be higher than 200 khz to get a higher sample rate. the adc module contains a prescaler, which generates an acceptable adc clock frequency from any cpu frequency above 100 khz. the presca ling is set by the adps bits in adcsra. the prescaler starts counting from the moment the adc is switched on by setting the aden bit in adcsra. the prescaler keeps running for as lo ng as the aden bit is set, and is continuously reset when aden is low. when initiating a single ended conversion by se tting the adsc bit in adcsra, the conversion starts at the following rising edge of the adc clock cycle. a normal conversion takes 13 adc clock cycles. the first conversion after the adc is switched on (aden in adcsra is set) takes 25 adc clock cycles in order to initialize the analog circuitry. the actual sample-and-hold takes place 1.5 adc clock cycles after the start of a normal conver- sion and 13.5 adc clock cycles after the start of an first conv ersion. when a conversion is complete, the result is written to the adc data re gisters, and adif is set. in single conversion mode, adsc is cleared simultaneously. the software may then set adsc again, and a new conversion will be init iated on the first rising adc clock edge. 7-bit adc prescaler adc clock source ck adps0 adps1 adps2 ck/128 ck/2 ck/4 ck/8 ck/16 ck/32 ck/64 reset aden start 267 4921e?auto?09/09 ata6602/ata6603 when auto triggering is used, the prescaler is reset when the trigger event occurs. this assures a fixed delay from the trigger event to the start of conversion. in this mode, the sample-and-hold takes place two adc clock cycles after the rising edge on the trigger source signal. three addi- tional cpu clock cycles are used for synchronization logic. in free running mode, a new conversion will be started immediately after the conversion com- pletes, while adsc remains high. for a summary of conversion times (see table 4-97 on page 268 ). figure 4-103. adc timing diagram, first conversi on (single conversion mode) figure 4-104. adc timing diagram, single conversion sign and msb of result lsb of result adc clock adsc sample & hold adif adch adcl cycle number aden 1 212 13 14 15 16 17 18 19 20 21 22 23 24 25 1 2 first conversion next conversion 3 mux and refs update mux and refs update conversion complete 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 3 sample & hold mux and refs update conversion complete mux and refs update 268 4921e?auto?09/09 ata6602/ata6603 figure 4-105. adc timing diagram, auto triggered conversion figure 4-106. adc timing diagram, free running conversion 1 2 3 4 5 6 7 8 9 10 11 12 13 sign and msb of result lsb of result adc clock trigger source adif adch adcl cycle number 12 one conversion next conversion conversion complete prescaler reset adate prescaler reset sample & hold mux and refs update table 4-97. adc conversion time condition sample & hold (cycles from start of conversion) conversion time (cycles) first conversion 13.5 25 normal conversions, single ended 1.5 13 auto triggered conversions 2 13.5 11 12 13 sign and msb of result lsb of result adc clock adsc adif adch adcl cycle number 12 one conversion next conversion 34 conversion complete sample & hold mux and refs update 269 4921e?auto?09/09 ata6602/ata6603 4.21.4 changing channel or reference selection the muxn and refs1:0 bits in the admux register are single buffered through a temporary register to which the cpu has random access. this ensures that the channels and reference selection only takes place at a safe point dur ing the conversion. the channel and reference selection is continuously updated until a conversion is started. once the conversion starts, the channel and reference selection is locked to ensure a sufficient sampling time for the adc. con- tinuous updating resumes in the last adc clock cycle before the conversion completes (adif in adcsra is set). note that the conversion star ts on the following rising adc clock edge after adsc is written. the user is thus advised not to write new channel or reference selection values to admux until one adc clock cycle after adsc is written. if auto triggering is used, the exact time of t he triggering event can be indeterministic. special care must be taken when updating the admux register, in order to control which conversion will be affected by the new settings. if both adate and aden is written to one, an interrupt event can occur at any time. if the admux register is changed in this period, the user cannot tell if the next conversion is based on the old or the new settings. admux can be safely updated in the following ways: a. when adate or aden is cleared. b. during conversion, minimum one adc clock cycle after the trigger event. c. after a conversion, before the interrupt flag used as trigger source is cleared. when updating admux in one of these conditions, the new settings will affect the next adc conversion. 4.21.4.1 adc input channels when changing channel selections, the user should observe the following guidelines to ensure that the correct channel is selected: in single conversion mode, always select the channel before starting the conversion. the chan- nel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the conversion to complete before changing the channel selection. in free running mode, always select the channel before starting the first conversion. the chan- nel selection may be changed one adc clock cycle after writing one to adsc. however, the simplest method is to wait for the first conversion to complete, and then change the channel selection. since the next conver sion has already started automati cally, the next result will reflect the previous channel selection. subsequent conversions will refl ect the new channel selection. 4.21.4.2 adc voltage reference the reference voltage for the adc (v ref ) indicates the conversion range for the adc. single ended channels that exceed v ref will result in code s close to 0x3ff. v ref can be selected as either av cc , internal 1.1v reference, or external aref pin. av cc is connected to the adc through a passive switch. the internal 1.1v reference is gener- ated from the internal bandgap reference (v bg ) through an internal amplifier. in either case, the external aref pin is directly connected to the adc, and the reference voltage can be made more immune to noise by connecting a capacitor between the aref pin and ground. v ref can also be measured at the aref pin with a high impedant voltmeter. note that v ref is a high impedant source, and only a capacitive load should be connected in a system. 270 4921e?auto?09/09 ata6602/ata6603 if the user has a fixed voltage source connected to the aref pin, the user may not use the other reference voltage options in the ap plication, as they will be shorte d to the external voltage. if no external voltage is applied to the aref pin, the user may switch between av cc and 1.1v as ref- erence selection. the first adc conversion result after switching reference voltage source may be inaccurate, and the user is advised to discard this result. 4.21.5 adc noise canceler the adc features a noise canceler that enables conversion during sleep mode to reduce noise induced from the cpu core and other i/o peripherals. the noise canceler can be used with adc noise reduction and idle mode. to make use of this feature, the following procedure should be used: a. make sure that the adc is enabled and is not busy converting. single conversion mode must be selected and the adc conversion complete interrupt must be enabled. b. enter adc noise reduction mode (or idle mode). the adc will start a conversion once the cpu has been halted. c. if no other interrupts occur before the adc conversion completes, the adc inter- rupt will wake up the cpu and execute the adc conversion complete interrupt routine. if another interrupt wakes up the cpu before the adc conversion is com- plete, that interrupt will be executed, and an adc conversion complete interrupt request will be generated when the adc conversion completes. the cpu will remain in active mode until a new sleep command is executed. note that the adc will not be automatically turned off when entering other sleep modes than idle mode and adc noise reduction mode. the user is advised to write zero to aden before enter- ing such sleep modes to avoid excessive power consumption. 4.21.5.1 analog input circuitry the analog input circuitry for singl e ended channels is illustrated in figure 4-107 on page 271 an analog source applied to adcn is subjected to the pin capacitance and input leakage of that pin, regardless of whether that channel is select ed as input for the adc. when the channel is selected, the source must drive the s/h capacito r through the series resistance (combined resis- tance in the input path). the adc is optimized for analog signals with an output impedance of approximately 10 k or less. if such a source is used, the sampling time will be negligible. if a source with higher imped- ance is used, the sampling time will depend on how long time the source nee ds to charge the s/h capacitor, with can vary widely. the user is recommended to only use low impedant sources with slowly varying signals, since this minimizes the required charge transfer to the s/h capacitor. signal components higher th an the nyquist frequency (f adc /2) should not be present for either kind of channels, to avoid distortion from unpredictable signal convolution. the user is advised to remove high frequency components with a low-pass filter before applying the signals as inputs to the adc. 271 4921e?auto?09/09 ata6602/ata6603 figure 4-107. analog input circuitry 4.21.5.2 analog noise canceling techniques digital circuitry inside and outside the device ge nerates emi which might affect the accuracy of analog measurements. if conversion accuracy is critical, the noise level can be reduced by applying the following techniques: a. keep analog signal paths as short as possible. make sure analog tracks run over the analog ground plane, and keep them well away from high-speed switching digi- tal tracks. b. the av cc pin on the device should be connected to the digital v cc supply voltage via an lc network as shown in figure 4-108 on page 272 . c. use the adc noise canceler function to reduce induced noise from the cpu. d. if any adc [3..0] port pins are used as digital outputs, it is essential that these do not switch while a conversion is in progress. however, using the 2-wire interface (adc4 and adc5) will only affect the conv ersion on adc4 and adc5 and not the other adc channels. adcn i ih 1..100 kw c s/h = 14 pf v cc /2 i il 272 4921e?auto?09/09 ata6602/ata6603 figure 4-108. adc power connections 4.21.5.3 adc accuracy definitions an n-bit single-ended adc converts a voltage linearly between gnd and v ref in 2 n steps (lsbs). the lowest code is read as 0, and the highest code is read as 2 n -1. several parameters describe the deviation from the ideal behavior: ? offset: the deviation of the first transition (0x000 to 0x001) compared to the ideal transition (at 0.5 lsb). ideal value: 0 lsb. gnd vcc pc5 (adc5/sc l) pc4 (adc4/sd a) pc3 (adc3) pc2 (adc2) pc1 (adc1) pc0 (adc0) adc7 gnd aref avcc adc6 pb5 10 mh 100 nf analog ground plane 273 4921e?auto?09/09 ata6602/ata6603 figure 4-109. offset error ? gain error: after adjusting for offset, the gain error is found as the deviation of the last transition (0x3fe to 0x3ff) compared to the ideal transition (at 1.5 lsb below maximum). ideal value: 0 lsb figure 4-110. gain error ? integral non-linearity (inl): after adjusting for offset and gain error, the inl is the maximum deviation of an actual transition compared to an ideal transition for any code. ideal value: 0 lsb. figure 4-111. integral non-linearity (inl) output code v ref input voltage ideal adc actual ad c offset error output code v ref input voltage ideal adc actual adc gain error output code v ref input voltage ideal adc actual adc inl 274 4921e?auto?09/09 ata6602/ata6603 ? differential non-linearity (dnl): the maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 lsb). ideal value: 0 lsb. figure 4-112. differential non-linearity (dnl) ? quantization error: due to the quantization of the input voltage into a finite number of codes, a range of input voltages (1 lsb wide) will code to the same value. always 0.5 lsb. ? absolute accuracy: the maximum deviation of an actual (unadjusted) transition compared to an ideal transition for any code. this is the compound effect of offset, gain error, differential error, non-linearity, and quantization error. ideal value: 0.5 lsb. output code 0x3ff 0x000 0 v ref input voltage dnl 1 lsb 275 4921e?auto?09/09 ata6602/ata6603 4.21.6 adc conversion result after the conversion is complete (adif is high ), the conversion result can be found in the adc result registers (adcl, adch). for single ended conversion, the result is where v in is the voltage on the selected input pin and v ref the selected voltage reference (see table 4-98 on page 275 and table 4-99 on page 276 ). 0x000 represents analog ground, and 0x3ff represents the selected reference voltage minus one lsb. 4.21.6.1 adc multiplexer selection register ? admux ? bit 7:6 ? refs1:0: reference selection bits these bits select the voltage reference for the adc, as shown in table 4-98 . if these bits are changed during a conversion, the change will no t go in effect until this conversion is complete (adif in adcsra is set). the internal voltage reference options may not be used if an external reference voltage is being applied to the aref pin. ? bit 5 ? adlar: adc left adjust result the adlar bit affects the presentation of the adc conversion result in the adc data reg- ister. write one to adlar to left adjust the result. otherwise, the result is right adjusted. changing the adlar bit will affect the adc da ta register immediately, regardless of any ongoing conversions. for a complete description of this bit (see ?the adc data register ? adcl and adch? on page 278 ). ? bit 4 ? res: reserved bit this bit is an unused bit in the ata660 2/ata6603, and will always read as zero. ? bits 3:0 ? mux3:0: analog channel selection bits the value of these bits selects which analog inputs are connected to the adc. see table 4-99 on page 276 for details. if these bits are changed durin g a conversion, the change will not go in effect until this conversion is complete (adif in adcsra is set). adc v in 1024 ? v ref ----------------------------- = bit 76543210 refs1 refs0 adlar ? mux3 mux2 mux1 mux0 admux read/write r/w r/w r/w r r/w r/w r/w r/w initial value00000000 table 4-98. voltage reference selections for adc refs1 refs0 voltage reference selection 0 0 aref, internal v ref turned off 01 av cc with external capacitor at aref pin 10reserved 1 1 internal 1.1v voltage reference wit h external capacitor at aref pin 276 4921e?auto?09/09 ata6602/ata6603 4.21.6.2 adc control and status register a ? adcsra ? bit 7 ? aden: adc enable writing this bit to one enables the adc. by writing it to zero, the adc is turned off. turning the adc off while a conversion is in pr ogress, will terminate this conversion. ? bit 6 ? adsc: adc start conversion in single conversion mode, write this bit to one to start each conversion. in free running mode, write this bit to one to start the first conversion. the first conversion after adsc has been written after the adc has been enabled, or if adsc is written at the same time as the adc is enabled, will take 25 adc clock cycles in stead of the normal 13. this first conversion performs initialization of the adc. adsc will read as one as long as a conversion is in prog ress. when the co nversion is com- plete, it returns to zero. writing zero to this bit has no effect. ? bit 5 ? adate: adc auto trigger enable when this bit is written to one, auto trigger ing of the adc is enabled. the adc will start a conversion on a positive edge of the selected trigger signal. the trigger source is selected by setting the adc trigger se lect bits, adts in adcsrb. table 4-99. input channel selections mux3..0 single ended input 0000 adc0 0001 adc1 0010 adc2 0011 adc3 0100 adc4 0101 adc5 0110 adc6 0111 adc7 1000 (reserved) 1001 (reserved) 1010 (reserved) 1011 (reserved) 1100 (reserved) 1101 (reserved) 1110 1.1v (v bg ) 1111 0v (gnd) bit 76543210 aden adsc adate adif adie adps2 adps1 adps0 adcsra read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 277 4921e?auto?09/09 ata6602/ata6603 ? bit 4 ? adif: adc interrupt flag this bit is set when an adc conversion completes and the data registers are updated. the adc conversion complete interrupt is executed if the adie bit and the i-bit in sreg are set. adif is cleared by hardware when exec uting the corresponding interrupt handling vec- tor. alternatively, adif is cl eared by writing a logical one to the flag. beware that if doing a read-modify-write on adcsra, a pending interrupt can be disabled. this also applies if the sbi and cbi instructions are used. ? bit 3 ? adie: adc interrupt enable when this bit is written to one and the i-bit in sreg is set, the adc conversion complete interrupt is activated. ? bits 2:0 ? adps2:0: adc prescaler select bits these bits determine the division factor between the system clock frequency and the input clock to the adc. table 4-100. adc prescaler selections adps2 adps1 adps0 division factor 000 2 001 2 010 4 011 8 100 16 101 32 110 64 111 128 278 4921e?auto?09/09 ata6602/ata6603 4.21.6.3 the adc data register ? adcl and adch adlar = 0 adlar = 1 when an adc conversion is complete, the result is found in these two registers. when adcl is read, the adc data register is not updated unt il adch is read. consequently, if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read adch. otherwise, adcl must be read first, then adch. the adlar bit in admux, and the muxn bits in admux affect the way the result is read from the registers. if adlar is set, the result is left adjusted. if adla r is cleared (default), the result is right adjusted. ? adc9:0: adc conversion result these bits represent the result fr om the conversion, as detailed in ?adc conversion result? on page 275 . bit 151413121110 9 8 ??????adc9adc8 adch adc7 adc6 adc5 adc4 adc3 adc2 adc1 adc0 adcl 76543210 read/write r r rrrrrr rrrrrrrr initial value00000000 00000000 bit 151413121110 9 8 adc9 adc8 adc7 adc6 adc5 adc4 adc3 adc2 adch adc1adc0??????adcl 76543210 read/write r r r rrrrr rrrrrrrr initial value00000000 00000000 279 4921e?auto?09/09 ata6602/ata6603 4.21.6.4 adc control and status register b ? adcsrb ? bit 7, 5:3 ? res: reserved bits these bits are reserved for futu re use. to ensure compatibility wi th future devices, these bits must be written to zero when adcsrb is written. ? bit 2:0 ? adts2:0: adc auto trigger source if adate in adcsra is written to one, the value of these bits selects which source will trig- ger an adc conversion. if adate is cleared, the adts2:0 settings will have no effect. a conversion will be triggered by the rising edge of the selected interrupt flag. note that switching from a trigger s ource that is cleared to a trigger source that is set, will generate a positive edge on the trigger signa l. if aden in adcsra is set, this will start a conversion. switching to free running mode (adts[2:0]=0) will not cause a trigger event, even if the adc interrupt flag is set . 4.21.6.5 digital input disable register 0 ? didr0 ? bits 7:6 ? res: reserved bits these bits are reserved for futu re use. to ensure compatibility wi th future devices, these bits must be written to zero when didr0 is written. ? bit 5..0 ? adc5d..adc0d: adc5..0 digital input disable when this bit is written logic one, the digital input buffer on the corresponding adc pin is dis- abled. the corresponding pin register bit will always read as zero when this bit is set. when an analog signal is applied to the adc5.. 0 pin and the digital input from this pin is not needed, this bit should be written logic one to reduce power consumption in the digital input buffer. note that adc pins adc7 and adc6 do not have digital input buffers, and therefore do not require digital input disable bits. bit 76543210 ? acme ? ? ? adts2 adts1 adts0 adcsrb read/write r r/w r r r r/w r/w r/w initial value 0 0 0 0 0 0 0 0 table 4-101. adc auto trigger source selections adts2 adts1 adts0 trigger source 0 0 0 free running mode 0 0 1 analog comparator 0 1 0 external interrupt request 0 0 1 1 timer/counter0 compare match a 1 0 0 timer/counter0 overflow 1 0 1 timer/counter1 compare match b 1 1 0 timer/counter1 overflow 1 1 1 timer/counter1 capture event bit 76543210 ? ? adc5d adc4d adc3d adc2d adc1d adc0d didr0 read/write r r r/w r/w r/w r/w r/w r/w initial value00000000 280 4921e?auto?09/09 ata6602/ata6603 4.22 debugwire on-c hip debug system 4.22.1 features ? complete program flow control ? emulates all on-chip func tions, both digital and analog, except reset pin ? real-time operation ? symbolic debugging support (both at c and assembler source level, or for other hlls) ? unlimited number of prog ram break points (using software break points) ? non-intrusive operation ? electrical characteristics identical to real device ? automatic configuration system ? high-speed operation ? programming of non-volatile memories 4.22.2 overview the debugwire on-chip debug system uses a one-wire, bi-directional interface to control the program flow, execute avr instructions in the cpu and to program the different non-volatile memories. 4.22.3 physical interface when the debugwire enable (dwen) fuse is programmed and lock bits are unprogrammed, the debugwire system within the target device is activated. the reset port pin is configured as a wire-and (open-drain) bi-directional i/o pin with pull-up enabled and becomes the commu- nication gateway between target and emulator. figure 4-113. the debugwire setup figure 4-113 shows the schematic of a target mcu, with debugwire enabled, and the emulator connector. the system clock is not affected by debugwire and will always be the clock source selected by the cksel fuses. vcc gnd dw(rese) dw 2.7 - 5.5 281 4921e?auto?09/09 ata6602/ata6603 when designing a system where debugwire will be used, the following observations must be made for correct operation: ? pull-up resistors on the dw/(reset) line must not be smaller than 10k . the pull-up resistor is not required for debugwire functionality. ? connecting the reset pin directly to v cc will not work. ? capacitors connected to th e reset pin must be disconne cted when using debugwire. ? all external reset sources must be disconnected. 4.22.4 software break points debugwire supports program memory break points by the avr break instruction. setting a break point in avr studio ? will insert a break instruction in the program memo ry. the instruc- tion replaced by the break instru ction will be stored. when program execution is continued, the stored instruction will be execut ed before continuing from the program memory. a break can be inserted manually by putting the break instruction in the program. the flash must be re-programmed each time a break point is changed. this is automatically handled by avr studio th rough the debugwire inte rface. the use of brea k points will therefore reduce the flash data retention. devices used for debugging purposes should not be shipped to end customers. 4.22.5 limitations of debugwire the debugwire communication pin (dw) is physica lly located on the same pin as external reset (reset). an external reset source is therefore not supported when the debugwire is enabled. the debugwire system accurately emulates all i/ o functions when running at full speed, i.e., when the program in the cpu is running. when the cpu is stopped, care must be taken while accessing some of the i/o registers via the debugger (avr studio). a programmed dwen fuse enable s some parts of the clock system to be running in all sleep modes. this will increase the power consumption while in sleep. thus, the dwen fuse should be disabled when debugwire is not used. 4.22.6 debugwire related register in i/o memory the following section describes the registers used with the debugwire. 4.22.6.1 debugwire data register ? dwdr the dwdr register provides a communication channel from the running program in the mcu to the debugger. this register is only accessible by the debugwire and can therefore not be used as a general purpose register in the normal operations. bit 76543210 dwdr[7:0] dwdr read/write r/w r/w r/w r/w r/w r/w r/w r/w initial value00000000 282 4921e?auto?09/09 ata6602/ata6603 4.23 boot loader support ? read-while-write self-programming, at a6602 and ata6603 in ata6602 and ata6603, the boot loader support provides a real read-while-write self-pro- gramming mechanism for downloading and uploading program code by the mcu itself. this feature allows flexible application software updat es controlled by the mcu using a flash-resi- dent boot loader program. the boot loader progr am can use any availa ble data interface and associated protocol to read code and write (progr am) that code into the flash memory, or read the code from the program memory. the program code within the boot loader section has the capability to write into the entire flash, includ ing the boot loader memory . the boot loader can thus even modify itself, and it can also erase itself from the code if the feature is not needed any- more. the size of the boot loader memory is configurable with fuses and the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to select di fferent levels of protection. 4.23.1 boot loader features ? read-while-write self-programming ? flexible boot memory size ? high security (separate boot lock bits for a flexible protection) ? separate fuse to select reset vector ? optimized page (1) size ? code efficient algorithm ? efficient read-modify-write support note: 1. a page is a section in the flash consisting of several bytes (see table 4-123 on page 304 ) used during programming. the page organiz ation does not affect normal operation. 4.23.2 application and boot loader flash sections the flash memory is organized in two main sections, the application section and the boot loader section (see figure 4-115 on page 285 ). the size of the different sections is configured by the bootsz fuses as shown in table 4-107 on page 296 and figure 4-115 on page 285 . these two sections can have different level of protection since they have different sets of lock bits. 4.23.2.1 application section the application section is the section of the flash that is used for storing the application code. the protection level for the application section can be selected by the application boot lock bits (boot lock bits 0), see table 4-103 on page 286 . the application section can never store any boot loader code since the spm instruction is disabled when executed from the application section. 4.23.2.2 bls ? boot loader section while the application section is used for storing the application code, the the boot loader soft- ware must be located in the bls since the spm instruction can initiate a programming when executing from the bls only. the spm instruct ion can access the entire flash, including the bls itself. the protection level for the boot loader section can be selected by the boot loader lock bits (boot lock bits 1), see table 4-104 on page 286 . 283 4921e?auto?09/09 ata6602/ata6603 4.23.3 read-while-write and no read-while-write flash sections whether the cpu supports read-while-write or if the cpu is halted during a boot loader soft- ware update is dependent on which address that is being programmed. in addition to the two sections that are configurable by the bootsz fuses as described above, the flash is also divided into two fixed sections, the re ad-while-write (rww) section and the no read-while-write (nrww) section. the limit between the rww- and nrww sections is given in table 4-108 on page 296 and figure 4-115 on page 285 . the main difference between the two sections is: ? when erasing or writing a page located inside the rww section, the nrww section can be read during the operation. ? when erasing or writing a page located inside the nrww section, the cpu is halted during the entire operation. note that the user software can never read any code that is located inside the rww section dur- ing a boot loader software operation. the syntax ?read-while-write section? refers to which section that is being programmed (erased or written), not which section that actually is being read during a boot loader software update. 4.23.3.1 rww ? read-while-write section if a boot loader software update is programming a page inside the rww section, it is possible to read code from the flash, but only code that is located in the nrww section. during an on-going programming, the software must ensure that the rww section never is being read. if the user software is trying to read code that is located inside the rww section (i.e., by a call/jmp/lpm or an interrupt) during programming, the software might end up in an unknown state. to avoid this, the interrupts should either be disabled or moved to the boot loader sec- tion. the boot loader section is always located in the nrww section. the rww section busy bit (rwwsb) in the store program memory cont rol and status register (spmcsr) will be read as logical one as long as the rww section is blocked for reading. after a programming is com- pleted, the rwwsb must be cleared by software before reading code located in the rww section. see ?store program memory control and status register ? spmcsr? on page 287 for details on how to clear rwwsb. 4.23.3.2 nrww ? no read-while-write section the code located in the nrww section can be read when the boot loader software is updating a page in the rww section. when the boot loader code updates the nrww section, the cpu is halted during the entire page erase or page write operation. table 4-102. read-while-write features which section does the z-pointer address during the programming? which section can be read during programming? is the cpu halted? read-while-write supported? rww section nrww section no yes nrww section none yes no 284 4921e?auto?09/09 ata6602/ata6603 figure 4-114. read-while-write versus no read-while-write read-while-write (rww) section no read-while-write (nrww) section z-pointer addresses rww section z-pointer addresses nrww section cpu is halted during the operation code located in nrww section can be read during the operation 285 4921e?auto?09/09 ata6602/ata6603 figure 4-115. memory sections note: 1. the parameters in the figure above are given in table 4-107 on page 296 . 0x0000 flashend program memory bootsz = '11' application flash section boot loader flash section flashend program memory bootsz = '10' 0x0000 program memory bootsz = '01' program memory bootsz = '00' application flash section boot loader flash section 0x0000 flashend application flash section flashend end rww start nrww application flash section boot loader flash section boot loader flash section end rww start nrww end rww start nrww 0x0000 end rww, end application start nrww, start boot loader application flash section application flash section application flash section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section read-while-write section no read-while-write section end application start boot loader end application start boot loader end application start boot loader 286 4921e?auto?09/09 ata6602/ata6603 4.23.4 boot loader lock bits if no boot loader capability is n eeded, the entire flash is available for application code. the boot loader has two separate sets of boot lock bits which can be set independently. this gives the user a unique flexibility to sele ct different levels of protection. the user can select: ? to protect the entire flash from a software update by the mcu. ? to protect only the boot loader flash section from a software update by the mcu. ? to protect only the application flash section from a software update by the mcu. ? allow software update in the entire flash. see table 4-103 and table 4-104 for further details. the boot lock bits can be set in software and in serial or parallel programming mode, but they can be cleared by a chip erase command only. the general write lock (lock bit mode 2) does not control the programming of the flash memory by spm instruction. similarly, the general read/write lock (lock bit mode 1) does not control reading nor writing by lpm/spm, if it is attempted. note: 1. ?1? means unprogrammed, ?0? means programmed note: 1. ?1? means unprogrammed, ?0? means programmed table 4-103. boot lock bit0 protection modes (application section) (1) blb0 mode blb02 blb01 protection 1 1 1 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader sect ion is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if in terrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. table 4-104. boot lock bit1 protection modes (boot loader section) (1) blb1 mode blb12 blb11 protection 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application sect ion is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts ar e disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts ar e disabled while executing from the boot loader section. 287 4921e?auto?09/09 ata6602/ata6603 4.23.5 entering the boot loader program entering the boot loader takes place by a jump or call from the application program. this may be initiated by a trigger such as a command received via usart, or spi interface. alternatively, the boot reset fuse can be programmed so that the reset vector is pointing to the boot flash start address after a reset. in this case, the boot loader is started after a reset. after the applica- tion code is loaded, the program can start execut ing the application code. note that the fuses cannot be changed by the mcu itself. this means that once the boot reset fuse is pro- grammed, the reset vector will always point to the boot loader reset and the fuse can only be changed through the serial or parallel programming interface. note: 1. ?1? means unprogrammed, ?0? means programmed 4.23.5.1 store program memory control and status register ? spmcsr the store program memory control and status register contains the control bits needed to con- trol the boot loader operations. ? bit 7 ? spmie: spm interrupt enable when the spmie bit is written to one, and the i-bit in the status register is set (one), the spm ready interrupt will be enab led. the spm ready interrupt will be executed as long as the selfprgen bit in the spmcsr register is cleared. ? bit 6 ? rwwsb: read-while-write section busy when a self-programming (page erase or page write) operation to the rww section is ini- tiated, the rwwsb will be set (one) by hardware. when the rwwsb bit is set, the rww section cannot be acce ssed. the rwwsb bit will be cleared if the rwwsre bit is written to one after a self-programming operation is completed. alternatively the rwwsb bit will automatically be cleared if a page load operation is initiated. ? bit 5 ? res: reserved bit this bit is a reserved bit in the ata6602/ata6603 and always read as zero. ? bit 4 ? rwwsre: read-while-write section read enable when programming (page erase or page write) to the rww section, the rww section is blocked for reading (the rwwsb will be set by hardware). to re-ena ble the rww section, the user software must wait until the programmi ng is completed (selfprgen will be cleared). then, if the rwwsre bit is written to one at the same time as selfprgen, the next spm instruction within four clock cycl es re-enables the rww section. the rww sec- tion cannot be re-enabled while the flash is busy with a page erase or a page write (selfprgen is set). if the rwwsre bit is written while the flash is being loaded, the flash load operation will abort and the data lo aded will be lost. table 4-105. boot reset fuse (1) bootrst reset address 1 reset vector = application reset (address 0x0000) 0 reset vector = boot loader reset (see table 4-107 on page 296 ) bit 7 6 5 4 3 2 1 0 spmie rwwsb ? rwwsre blbset pgwrt pgers selfprgen spmcsr read/write r/w r r r/w r/w r/w r/w r/w initial value 0 0 0 0 0 0 0 0 288 4921e?auto?09/09 ata6602/ata6603 ? bit 3 ? blbset: boot lock bit set if this bit is written to one at the same time as selfprgen, the next spm instruction within four clock cycles sets boot lock bits and memo ry lock bits, acco rding to the data in r0. the data in r1 and the address in the z-pointer are ignored. the blbset bit will automatically be cleared upon completion of the lock bit set, or if no spm instruction is executed within four clock cycles. an lpm instruction within three cycles a fter blbset and selfprgen are set in the spmcsr register, will read either the lock bits or the fuse bits (depending on z0 in the z-pointer) into the destination register. see ?reading the fuse and lock bits from software? on page 292 for details. ? bit 2 ? pgwrt: page write if this bit is written to one at the same time as selfprgen, the next spm instruction within four clock cycles executes page write, with the data stored in the temporary buffer. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgwrt bit will auto-clear upon completion of a page write, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 1 ? pgers: page erase if this bit is written to one at the same time as selfprgen, the next spm instruction within four clock cycles executes page erase. the page address is taken from the high part of the z-pointer. the data in r1 and r0 are ignored. the pgers bit will auto-clear upon comple- tion of a page erase, or if no spm instruction is executed within four clock cycles. the cpu is halted during the entire page write operation if the nrww section is addressed. ? bit 0 ? selfprgen: self programming enable this bit enables the spm instruction for the next four clock cycles. if written to one together with either rwwsre, blbset, pgwrt or pgers, the follo wing spm instru ction will have a special meaning, see description above. if on ly selfprgen is written, the following spm instruction will store the valu e in r1:r0 in the temporary page buffer addressed by the z-pointer. the lsb of the z-pointer is i gnored. the selfprgen bit will auto-clear upon completion of an spm instruction, or if no spm instruction is executed within four clock cycles. during page erase and page write, the selfprgen bit remains high until the operation is completed. writing any other combination than ?10001?, ?01001?, ?00101?, ?00011? or ?00001? in the lower five bits will have no effect. 289 4921e?auto?09/09 ata6602/ata6603 4.23.6 addressing the flash during self-programming the z-pointer is used to address the spm commands. since the flash is organized in pages (see table 4-123 on page 304 ), the program counter can be treated as having two different sections. one sect ion, consisting of the least significant bits, is addressing the words within a page, while the most significant bits are addressing the pages. this is1 shown in figure 4-116 . note that the page erase and page write operations are addressed independently. therefore it is of major importance that the boot loader software addresses the same page in both the page erase and page write operation. once a program- ming operation is initiated, the address is latched and the z-pointer can be used for other operations. the only spm operation that does not use the z-pointer is setting the boot loader lock bits. the content of the z-pointer is ignored and will have no effect on the operation. the lpm instruction does also use the z-pointer to store the address. since this instruction addresses the flash byte-by-byte, also the lsb (bit z0) of the z-pointer is used. figure 4-116. addressing the flash during spm (1) note: 1. the different variables used in figure 4-116 are listed in table 4-109 on page 296 . bit 151413121110 9 8 zh (r31) z15 z14 z13 z12 z11 z10 z9 z8 zl (r30) z7 z6 z5 z4 z3 z2 z1 z0 76543210 program memory 0 1 15 z - register bit 0 zpagemsb word address within a page page address within the flash zpcmsb instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter 290 4921e?auto?09/09 ata6602/ata6603 4.23.7 self-programming the flash the program memory is updated in a page by page fashion. before programming a page with the data stored in the temporary page buffer, the page must be erased. the temporary page buf- fer is filled one word at a time using spm and the buffer can be filled either before the page erase command or between a page erase and a page write operation: alternative 1, fill the bu ffer before a page erase ? fill temporary page buffer ? perform a page erase ? perform a page write alternative 2, fill the bu ffer after page erase ? perform a page erase ? fill temporary page buffer ? perform a page write if only a part of the page needs to be changed, the rest of the page must be stored (for example in the temporary page buffer) before the erase, and then be rewritten. when using alternative 1, the boot loader provides an effective read-modify-write feature which allows the user software to first read the page, do the necessary changes, and then write back the modified data. if alter- native 2 is used, it is not possible to read the old data while loading since the page is already erased. the temporary page buffer can be accessed in a random sequence. it is essential that the page address used in both the page erase a nd page write operation is addressing the same page. see ?simple assembly code example for a boot loader? on page 294 for an assembly code example. 4.23.7.1 performing page erase by spm to execute page erase, set up the address in the z-pointer, write ?x0000011? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage in the z-register. other bits in the z-pointer will be ignored during this operation. ? page erase to the rww section: the nrww section can be read during the page erase. ? page erase to the nrww section: the cpu is halted during the operation. 4.23.7.2 filling the temporary buffer (page loading) to write an instruction word, set up the address in the z-pointer and data in r1:r0, write ?00000001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the content of pcword in the z-register is used to address the data in the temporary buffer. the temporary buffer will auto-erase after a page write operation or by writing the rwwsre bit in spmcsr. it is also erased after a system reset. note that it is not possible to write more than one time to each address without erasing the temporary buffer. if the eeprom is written in the middle of an spm page load operation, all data loaded will be lost. 291 4921e?auto?09/09 ata6602/ata6603 4.23.7.3 performing a page write to execute page write, set up the address in the z-pointer, write ?x0000101? to spmcsr and execute spm within four clock cycles after writing spmcsr. the data in r1 and r0 is ignored. the page address must be written to pcpage. other bits in the z-pointer must be written to zero during this operation. ? page write to the rww section: the nrww section can be read during the page write. ? page write to the nrww section: the cpu is halted during the operation. 4.23.7.4 using the spm interrupt if the spm interrupt is en abled, the spm interrupt will genera te a constant in terrupt when the selfprgen bit in spmcsr is cleared. this means that the interrupt can be used instead of polling the spmcsr register in software. when using the spm interrupt, the interrupt vectors should be moved to the bls section to avoid that an interrupt is accessing the rww section when it is blocked for reading. how to move the interrupts is described in ?watchdog timer? on page 72 . 4.23.7.5 consideration while updating bls special care must be taken if the user allows the boot loader section to be updated by leaving boot lock bit11 unprogrammed. an accidental write to the boot loader itself can corrupt the entire boot loader, and further software updates might be impossible. if it is not necessary to change the boot loader software itself, it is recommended to program the boot lock bit11 to protect the boot loader software from any internal software changes. 4.23.7.6 prevent reading the rww section during self-programming during self-programming (either page erase or page write), the rww section is always blocked for reading. the user software itself must prevent that this section is addressed during the self programming operation. the rwwsb in the spmcsr will be set as long as the rww section is busy. during self-programming the interrupt vector table should be moved to the bls as described in ?watchdog timer? on page 72 , or the interrupts must be disabled. before addressing the rww section after the programming is completed, the user software must clear the rwwsb by writing the rwwsre. see ?simple assembly code example for a boot loader? on page 294 for an example. 4.23.7.7 setting the boot loader lock bits by spm to set the boot loader lock bits, write the desired data to r0, write ?x0001001? to spmcsr and execute spm within four clock cycles after writing spmcsr. the only accessible lock bits are the boot lock bits that may prevent the a pplication and boot loader section from any soft- ware update by the mcu. see table 4-103 on page 286 and table 4-104 on page 286 for how the different settings of the boot loader bits affect the flash access. bit 76543210 r0 1 1 blb12 blb11 blb02 blb01 1 1 292 4921e?auto?09/09 ata6602/ata6603 if bits 5..2 in r0 are cleared (zero), the corresponding boot lock bit will be programmed if an spm instruction is executed within four cy cles after blbset and selfprgen are set in spmcsr. the z-pointer is don?t care during this oper ation, but for future compatibility it is rec- ommended to load the z-pointer with 0x0001 (same as used for reading the lo ck bits). for future compatibility it is also recommende d to set bits 7, 6, 1, and 0 in r0 to ?1? when writing the lock bits. when programming the lock bits the entire flash can be read during the operation. 4.23.7.8 eeprom write prev ents writing to spmcsr note that an eeprom write oper ation will block all software progra mming to flash. reading the fuses and lock bits from software will also be prevented during the eeprom write operation. it is recommended that the user checks the status bit (eepe) in the eecr register and verifies that the bit is cleared before writing to the spmcsr register. 4.23.7.9 reading the fuse and lock bits from software it is possible to read both the fuse and lock bits from software. to read the lock bits, load the z-pointer with 0x0001 and set the blbset and selfprgen bits in spmcsr. when an lpm instruction is executed within three cpu cycles af ter the blbset and selfp rgen bits are set in spmcsr, the value of the lock bits will be loaded in the destination register. the blbset and selfprgen bits will auto-clear upon completion of reading the lock bits or if no lpm instruction is executed within three cpu cycl es or no spm instruction is executed within four cpu cycles. when blbset and se lfprgen are cleared, lpm will wo rk as described in the instruction set manual. the algorithm for reading the fuse low byte is similar to the one described above for reading the lock bits. to read the fuse low byte, load the z-pointer with 0x0000 and set the blbset and selfprgen bits in spmcsr. when an lpm instruction is executed within three cycles after the blbset and selfprgen bits are set in the spmcsr, the value of the fuse low byte (flb) will be loaded in the destination register as shown below. refer to table 4-116 on page 300 for a detailed description and mapping of the fuse low byte. similarly, when reading the fuse high byte, load 0x0003 in the z-pointer. when an lpm instruc- tion is executed within three cycles after t he blbset and selfprgen bits are set in the spmcsr, the value of the fuse high byte (fhb ) will be loaded in the destination register as shown below. refer to table 4-117 on page 300 for detailed description and mapping of the fuse high byte. bit 76543210 rd ? ? blb12 blb11 blb02 blb01 lb2 lb1 bit 76543210 rd flb7 flb6 flb5 flb4 flb3 flb2 flb1 flb0 bit 76543210 rd fhb7 fhb6 fhb5 fhb4 fhb3 fhb2 fhb1 fhb0 293 4921e?auto?09/09 ata6602/ata6603 when reading the extended fuse byte, load 0x0002 in the z-pointer. when an lpm instruction is executed within th ree cycles after the blbset and selfprg en bits are set in the spmcsr, the value of the exten ded fuse byte (efb) will be loaded in the destination r egister as shown below. refer to table 4-116 on page 300 for detailed description and mapping of the extended fuse byte. fuse and lock bits that are programmed, will be read as zero. fuse and lock bits that are unprogrammed, will be read as one. 4.23.7.10 preventing flash corruption during periods of low v cc , the flash program can be corrupted because the supply voltage is too low for the cpu and the flash to operate properly. these issues are the same as for board level systems using the flash, and the same design solutions should be applied. a flash program corruption can be caused by two situ ations when the voltage is too low. first, a regular write sequence to the flash requires a minimum voltage to operate correctly. secondly, the cpu itself can execute instruct ions incorrectly, if the supply voltage for executing instructions is too low. flash corruption can easily be avoided by following these design recommendations (one is sufficient): 1. if there is no need for a boot loader update in the system, program the boot loader lock bits to prevent any boot loader software updates. 2. keep the avr reset active (low) during peri ods of insufficient power supply voltage. this can be done by enabling the internal brown-out detector (bod) if the operating voltage matches the detection level. if not, an external low v cc reset protection circuit can be used. if a reset occurs while a write operation is in progress, the write operation will be completed provided that the power supply voltage is sufficient. 3. keep the avr core in power-down sleep mode during periods of low v cc . this will pre- vent the cpu from attempting to decode and execute instructions, effectively protecting the spmcsr register and thus the flash from unintentional writes. 4.23.7.11 programming time for flash when using spm the calibrated rc oscillator is used to time flash accesses. table 4-106 shows the typical pro- gramming time for flash accesses from the cpu. bit 76543210 rd ? ? ? ? efb3 efb2 efb1 efb0 table 4-106. spm programming time symbol min programming time max programming time flash write (page erase, page write, and write lock bits by spm) 3.7 ms 4.5 ms 294 4921e?auto?09/09 ata6602/ata6603 4.23.7.12 simple assembly code example for a boot loader ;-the routine writes one page of data from ram to flash ; the first data location in ram is pointed to by the y pointer ; the first data location in flash is pointed to by the z-pointer ;-error handling is not included ;-the routine must be placed inside the boot space ; (at least the do_spm sub routine). only code inside nrww section can ; be read during self-programming (page erase and page write). ;-registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24), ; loophi (r25), spmcrval (r20) ; storing and restoring of registers is not included in the routine ; register usage can be optimized at the expense of code size ;-it is assumed that either the interrupt table is moved to the boot ; loader section or that the interrupts are disabled. .equ pagesizeb = pagesize*2 ;pagesizeb is page size in bytes, not words .org smallbootstart write_page: ; page erase ldi spmcrval, (1< 297 4921e?auto?09/09 ata6602/ata6603 4.23.7.14 ata6603 boot loader parameters in table 4-110 through table 4-112 , the parameters used in the description of the self program- ming are given. note: the different bootsz fuse configurations are shown in figure 4-115 on page 285 . for details about these two section, see ?nrww ? no read-while-write section? on page 283 and ?rww ? read-while-write section? on page 283 . note: 1. z15:z14: always ignored z0: should be zero for all spm commands, byte select for the lpm instruction. see ?addressing the flash during self-programming? on page 289 for details about the use of z-pointer during self-programming. table 4-110. boot size configuration, ata6603 bootsz1 bootsz0 boot size pages application flash section boot loader flash section end application section boot reset address (start boot loader section) 11 128 words 2 0x0000 - 0x1f7f 0x1f80 - 0x1fff 0x1f7f 0x1f80 10 256 words 4 0x0000 - 0x1eff 0x1f00 - 0x1fff 0x1eff 0x1f00 01 512 words 8 0x0000 - 0x1dff 0x1e00 - 0x1fff 0x1dff 0x1e00 00 1024 words 16 0x0000 - 0x1bff 0x1c00 - 0x1fff 0x1bff 0x1c00 table 4-111. read-while-write limit, ata6603 section pages address read-while-write section (rww) 112 0x0000 - 0x1bff no read-while-write section (nrww) 16 0x1c00 - 0x1fff table 4-112. explanation of different variables used in figure 4-116 on page 289 and the mapping to the z-pointer, ata6603 variable corresponding z-value (1) description pcmsb 12 most significant bit in the program counter. (the program counter is 12 bits pc[11:0]) pag e m s b 5 most significant bit which is used to address the words within one page (64 words in a page requires 6 bits pc [5:0]) zpcmsb z13 bit in z-register that is mapped to pcmsb. because z0 is not used, the zpcmsb equals pcmsb + 1. zpagemsb z6 bit in z-register that is mapped to pagemsb. because z0 is not used, the zpagemsb equals pagemsb + 1. pcpage pc[12:6] z13:z7 program counter page address: page select, for page erase and page write pcword pc[5:0] z6:z1 program counter word address: word select, for filling temporary buffer (must be zero during page write operation) 298 4921e?auto?09/09 ata6602/ata6603 4.24 memory programming 4.24.1 program and data memory lock bits the ata6602/ata6603 provides six lock bits which can be left unprogrammed (?1?) or can be programmed (?0?) to obtain the additional features listed in table 4-114 . the lock bits can only be erased to ?1? with the chip erase command. the spm instruction is enabled for the whole flash if the selfprgen fuse is programmed (?0?), otherwise it is disabled. notes: 1. ?1? means unprogrammed, ?0? means programmed 2. only on ata6602/ata6603 notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed table 4-113. lock bit byte (1) lock bit byte bit no de scription default value 7 ? 1 (unprogrammed) 6 ? 1 (unprogrammed) blb12 (2) 5 boot lock bit 1 (unprogrammed) blb11 (2) 4 boot lock bit 1 (unprogrammed) blb02 (2) 3 boot lock bit 1 (unprogrammed) blb01 (2) 2 boot lock bit 1 (unprogrammed) lb2 1 lock bit 1 (unprogrammed) lb1 0 lock bit 1 (unprogrammed) table 4-114. lock bit protection modes (1)(2) memory lock bits protection type lb mode lb2 lb1 1 1 1 no memory lock features enabled. 210 further programming of the flas h and eeprom is disabled in parallel and serial programming mode. the fuse bits are locked in both serial and parallel programming mode. (1) 300 further programming and verifi cation of the flash and eeprom is disabled in parallel and serial programming mode. the boot lock bits and fuse bits are locked in both serial and parallel programming mode. (1) 299 4921e?auto?09/09 ata6602/ata6603 notes: 1. program the fuse bits and boot lock bits before programming the lb1 and lb2. 2. ?1? means unprogrammed, ?0? means programmed 4.24.2 fuse bits the ata6602/ata6603 has three fuse bytes. table 4-116 to table 4-118 on page 301 describe briefly the functionality of all the fuses and how they are mapped into the fuse bytes. note that the fuses are read as logical zero, ?0?, if they are programmed. table 4-115. lock bit protection modes (1)(2) . only ata6602/ata6603. blb0 mode blb02 blb01 1 1 1 no restrictions for spm or lpm accessing the application section. 2 1 0 spm is not allowed to write to the application section. 300 spm is not allowed to write to the application section, and lpm executing from the boot loader sect ion is not allowed to read from the application section. if interrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. 401 lpm executing from the boot loader section is not allowed to read from the application section. if in terrupt vectors are placed in the boot loader section, interrupts are disabled while executing from the application section. blb1 mode blb12 blb11 111 no restrictions for spm or lpm accessing the boot loader section. 2 1 0 spm is not allowed to write to the boot loader section. 300 spm is not allowed to write to the boot loader section, and lpm executing from the application sect ion is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts ar e disabled while executing from the boot loader section. 401 lpm executing from the application section is not allowed to read from the boot loader section. if interrupt vectors are placed in the application section, interrupts ar e disabled while executing from the boot loader section. 300 4921e?auto?09/09 ata6602/ata6603 note: 1. the default value of bootsz1..0 results in maximum boot size. see table 4-119 on page 303 for details. notes: 1. see ?alternate functions of port c? on page 99 for description of rstdisbl fuse. 2. the spien fuse is not accessible in serial programming mode. 3. see ?watchdog timer control register - wdtcsr? on page 76 for details. 4. see table 4-21 on page 69 for bodlevel fuse decoding. table 4-116. extended fuse byte for ata6602/ata6603 extended fuse byte bit no description default value ?7?1 ?6?1 ?5?1 ?4?1 ?3?1 bootsz1 2 select boot size (see table 113 for details) 0 (programmed) (1) bootsz0 1 select boot size (see table 113 for details) 0 (programmed) (1) bootrst 0 select reset vector 1 (unprogrammed) table 4-117. fuse high byte high fuse byte bit no description default value rstdisbl (1) 7 external reset disable 1 (unprogrammed) dwen 6 debugwire enable 1 (unprogrammed) spien (2) 5 enable serial program and data downloading 0 (programmed, spi programming enabled) wdton (3) 4 watchdog timer always on 1 (unprogrammed) eesave 3 eeprom memory is preserved through the chip erase 1 (unprogrammed), eeprom not reserved bodlevel2 (4) 2 brown-out detector trigger level 1 (unprogrammed) bodlevel1 (4) 1 brown-out detector trigger level 1 (unprogrammed) bodlevel0 (4) 0 brown-out detector trigger level 1 (unprogrammed) 301 4921e?auto?09/09 ata6602/ata6603 note: 1. the default value of sut1..0 results in maximum start-up time for the default clock source. see table 4-12 on page 55 for details. 2. the default setting of cksel3..0 results in internal rc oscillator @ 8 mhz. see table 4-11 on page 55 for details. 3. the ckout fuse allows the system cl ock to be output on portb0. see ?clock output buffer? on page 58 for details. 4. see ?system clock prescaler? on page 58 for details. the status of the fuse bits is not affected by chip erase. note that the fuse bits are locked if lock bit1 (lb1) is programmed. program the fuse bits before programming the lock bits. 4.24.2.1 latching of fuses the fuse values are latched when the device enters programming mode and changes of the fuse values will have no effect until the part leaves programming mode. this does not apply to the eesave fuse which will take effect once it is programmed. the fuse s are also latched on power-up in normal mode. 4.24.3 signature bytes all atmel microcontrollers have a three-byte signature code which identifies the device. this code can be read in both serial and parallel mode, also when the device is locked. the three bytes reside in a separate address space. 4.24.3.1 ata6602 signature bytes 1. 0x000: 0x1e (indicates manufactured by atmel). 2. 0x001: 0x93 (indicates 8kb flash memory). 3. 0x002: 0x0a (indicates ata660 2 device when 0x001 is 0x93). 4.24.3.2 ata6603 signature bytes 1. 0x000: 0x1e (indicates manufactured by atmel). 2. 0x001: 0x94 (indicates 16kb flash memory). 3. 0x002: 0x06 (indicates ata6603 device when 0x001 is 0x94). table 4-118. fuse low byte low fuse byte bit no de scription default value ckdiv8 (4) 7 divide clock by 8 0 (programmed) ckout (3) 6 clock output 1 (unprogrammed) sut1 5 select start-up time 1 (unprogrammed) (1) sut0 4 select start-up time 0 (programmed) (1) cksel3 3 select clock source 0 (programmed) (2) cksel2 2 select clock source 0 (programmed) (2) cksel1 1 select clock source 1 (unprogrammed) (2) cksel0 0 select clock source 0 (programmed) (2) 302 4921e?auto?09/09 ata6602/ata6603 4.24.4 calibration byte the ata6602/ata6603 has a byte calibration value for the internal rc oscillator. this byte resides in the high byte of address 0x000 in th e signature address space. during reset, this byte is automatically written into the osccal regist er to ensure correct frequency of the calibrated rc oscillator. 4.24.5 parallel programming parameters, pin mapping, and commands this section describes how to parallel program and verify flash program memory, eeprom data memory, memory lock bits, and fuse bits in the ata6602/ata6603. pulses are assumed to be at least 250 ns unless otherwise noted. 4.24.5.1 signal names in this section, some pins of the ata6602/ata 6603 are referenced by signal names describing their functionality during parallel programming (see figure 4-117 and table 4-119 on page 303 ). pins not described in the following table are referenced by pin names. the xa1/xa0 pins determine the action executed when the xtal1 pin is given a positive pulse. the bit coding is shown in table 4-121 on page 303 . when pulsing wr or oe , the command loaded determines the action executed. the different commands are shown in table 4-122 on page 303 . figure 4-117. parallel programming vcc +5v gnd xtal1 pd1 pd2 pd3 pd4 pd5 pd6 pc[1:0]:pb[5:0] dat a reset pd7 +12 v bs1 xa0 xa1 oe rdy/bsy pagel pc2 wr bs2 avcc +5v 303 4921e?auto?09/09 ata6602/ata6603 table 4-119. pin name mapping signal name in programming mode pin name i/o function rdy/bsy pd1 o 0: device is busy programming, 1: device is ready for new command oe pd2 i output enable (active low) wr pd3 i write pulse (active low) bs1 pd4 i byte select 1 (?0? selects low byte, ?1? selects high byte) xa0 pd5 i xtal action bit 0 xa1 pd6 i xtal action bit 1 pagel pd7 i program memory and eeprom data page load bs2 pc2 i byte select 2 (?0? selects low byte, ?1? selects 2?nd high byte) data {pc[1:0]: pb[5:0]} i/o bi-directional data bus (output when oe is low) table 4-120. pin values used to enter programming mode pin symbol value pagel prog_enable[3] 0 xa1 prog_enable[2] 0 xa0 prog_enable[1] 0 bs1 prog_enable[0] 0 table 4-121. xa1 and xa0 coding xa1 xa0 action when xtal1 is pulsed 00 load flash or eeprom address (high or low address byte determined by bs1). 0 1 load data (high or low data byte for flash determined by bs1). 1 0 load command 1 1 no action, idle table 4-122. command byte bit coding command byte command executed 1000 0000 chip erase 0100 0000 write fuse bits 0010 0000 write lock bits 0001 0000 write flash 0001 0001 write eeprom 0000 1000 read signature bytes and calibration byte 0000 0100 read fuse and lock bits 0000 0010 read flash 0000 0011 read eeprom 304 4921e?auto?09/09 ata6602/ata6603 4.24.6 serial programming pin mapping 4.24.7 parallel programming 4.24.7.1 enter programming mode the following algorithm puts the devi ce in parallel programming mode: 1. apply 4.5 - 5.5v between v cc and gnd. 2. set reset to ?0? and toggle xtal1 at least six times. 3. set the prog_enable pins listed in table 4-120 on page 303 to ?0000? and wait at least 100 ns. 4. apply 11.5 - 12.5v to reset . any activity on prog_enable pins within 100 ns after +12v has been applied to reset , will cause the device to fail entering programming mode. 5. wait at least 50 s before sending a new command. table 4-123. no. of words in a page and no. of pages in the flash device flash size page size pcword no. of pages pcpage pcmsb ata6602 4k words (8k bytes) 32 words pc[4:0] 128 pc[11:5] 11 ata6603 8k words (16k bytes) 64 words pc[5:0] 128 pc[12:6] 12 table 4-124. no. of words in a page and no. of pages in the eeprom device eeprom size page size pcword no. of pages pcpage eeamsb ata6602 512 bytes 4 bytes eea[1:0] 128 eea[8:2] 8 ata6603 512 bytes 4 bytes eea[1:0] 128 eea[8:2] 8 table 4-125. pin mapping serial programming symbol pins i/o description mosi pb3 i serial data in miso pb4 o serial data out sck pb5 i serial clock 305 4921e?auto?09/09 ata6602/ata6603 4.24.7.2 considerations for efficient programming the loaded command and address are retained in the device during programming. for efficient programming, the following should be considered. ? the command needs only be loaded once when writing or reading multiple memory locations. ? skip writing the data value 0xff, that is the contents of the entire eeprom (unless the eesave fuse is programmed) and flash after a chip erase. ? address high byte needs only be loaded before programming or reading a new 256 word window in flash or 256 byte eeprom. this consideration also applies to signature bytes reading. 4.24.7.3 chip erase the chip erase will erase the flash and eeprom (1) memories plus lock bits. the lock bits are not reset until the program memory has been completely erased. the fuse bits are not changed. a chip erase must be perfor med before the flas h and/or eeprom are reprogrammed. note: 1. the eeprpom memory is preserved during ch ip erase if the eesave fuse is programmed. load command ?chip erase? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?1000 0000?. this is the command for chip erase. 4. give xtal1 a positive pulse. this loads the command. 5. give wr a negative pulse. this starts the chip erase. rdy/bsy goes low. 6. wait until rdy/bsy goes high before loading a new command. 4.24.7.4 programming the flash the flash is organized in pages (see table 4-123 on page 304 ). when programming the flash, the program data is latched into a page buffer. this allows one page of program data to be pro- grammed simultaneously. the following procedure describes how to program the entire flash memory: a. load command ?write flash? 1. set xa1, xa0 to ?10?. this enables command loading. 2. set bs1 to ?0?. 3. set data to ?0001 0000?. this is the command for write flash. 4. give xtal1 a positive pulse. this loads the command. b. load address low byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?0?. this selects low address. 3. set data = address low byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address low byte. 306 4921e?auto?09/09 ata6602/ata6603 c. load data low byte 1. set xa1, xa0 to ?01?. this enables data loading. 2. set data = data low byte (0x00 - 0xff). 3. give xtal1 a positive pulse. this loads the data byte. d. load data high byte 1. set bs1 to ?1?. this selects high data byte. 2. set xa1, xa0 to ?01?. this enables data loading. 3. set data = data high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the data byte. e. latch data 1. set bs1 to ?1?. this selects high data byte. 2. give pagel a positive pulse. this latches the data bytes (see figure 4-119 on page 307 for signal waveforms). f. repeat b through e until the entire buffer is filled or until all data within the page is loaded. while the lower bits in the address are mapped to words within the page, the higher bits address the pages within the flash. this is illustrated in figure 4-118 on page 307 . note that if less than eight bits are required to address words in the page (pagesize < 256), the most significant bit(s) in the address low byte are used to address the page when performing a page write. g. load address high byte 1. set xa1, xa0 to ?00?. this enables address loading. 2. set bs1 to ?1?. this selects high address. 3. set data = address high byte (0x00 - 0xff). 4. give xtal1 a positive pulse. this loads the address high byte. h. program page 1. give wr a negative pulse. this starts programming of the entire page of data. rdy/bsy goes low. 2. wait until rdy/bsy goes high (see figure 4-119 on page 307 for signal waveforms). i. repeat b through h until the entire flas h is programmed or until all data has been programmed. j. end page programming 1. 1. set xa1, xa0 to ?10?. this enables command loading. 2. set data to ?0000 0000?. this is the command for no operation. 3. give xtal1 a positive pulse. this loads the command, and the internal write signals are reset. 307 4921e?auto?09/09 ata6602/ata6603 figure 4-118. addressing the flash which is organized in pages (1) note: 1. pcpage and pcword are listed in table 4-123 on page 304 . figure 4-119. programming the flash waveforms (1) note: 1. ?xx? is do not care. the letters refer to the programming description above. program memory word address within a page page address within the flash instruction word pag e pcword[pagemsb:0]: 00 01 02 pageend pag e pcword pcpage pcmsb pagemsb program counter rdy/bsy wr oe reset +12v pagel bs2 0x10 addr. low addr. high data data low data high addr. low data low data high xa1 xa0 bs1 xtal1 xx xx xx abcdebcdegh f 308 4921e?auto?09/09 ata6602/ata6603 4.24.7.5 programming the eeprom the eeprom is organized in pages (see table 4-124 on page 304 ). when programming the eeprom, the program data is latche d into a page buffer. this al lows one page of data to be programmed simultaneously. th e programming algorithm for th e eeprom data memory is as follows (refer to ?programming the flash? on page 305 for details on command, address and data loading): 1. a: load command ?0001 0001?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. c: load data (0x00 - 0xff). 5. e: latch data (give pagel a positive pulse). k: repeat 3 through 5 until the entire buffer is filled. l: program eeprom page 1. set bs1 to ?0?. 2. give wr a negative pulse. this starts prog ramming of the eeprom page. rdy/bsy goes low. 3. wait until to rdy/bsy goes high before programming the next page (see figure 4-120 for signal waveforms). figure 4-120. programming the eeprom waveforms 4.24.7.6 reading the flash the algorithm for reading the flash memory is as follows (refer to ?programming the flash? on page 305 for details on command and address loading): 1. a: load command ?0000 0010?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the flash word low byte can now be read at data. 5. set bs1 to ?1?. the flash word high byte can now be read at data. 6. set oe to ?1?. rdy/bsy wr oe reset +12v pagel bs2 0x11 addr. high data addr. low data addr. low data xx xa1 xa0 bs1 xtal1 xx ag bceb c el k 309 4921e?auto?09/09 ata6602/ata6603 4.24.7.7 reading the eeprom the algorithm for reading the eeprom memory is as follows (refer to ?programming the flash? on page 305 for details on command and address loading): 1. a: load command ?0000 0011?. 2. g: load address high byte (0x00 - 0xff). 3. b: load address low byte (0x00 - 0xff). 4. set oe to ?0?, and bs1 to ?0?. the eeprom data byte can now be read at data. 5. set oe to ?1?. 4.24.7.8 programming the fuse low bits the algorithm for programming the fuse low bits is as follows (refer to ?programming the flash? on page 305 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. give wr a negative pulse and wait for rdy/bsy to go high. 4.24.7.9 programming the fuse high bits the algorithm for programming the fuse high bits is as follows (refer to ?programming the flash? on page 305 for details on command and data loading): 1. a: load command ?0100 0000?. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. set bs1 to ?1? and bs2 to ?0?. this selects high data byte. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. set bs1 to ?0?. this selects low data byte. 4.24.7.10 programming the extended fuse bits the algorithm for programming the extended fuse bits is as follows (refer to ?programming the flash? on page 305 for details on command and data loading): 1. 1. a: load command ?0100 0000?. 2. 2. c: load data low byte. bit n = ?0? programs and bit n = ?1? erases the fuse bit. 3. 3. set bs1 to ?0? and bs2 to ?1?. this selects extended data byte. 4. 4. give wr a negative pulse and wait for rdy/bsy to go high. 5. 5. set bs2 to ?0?. this selects low data byte. 310 4921e?auto?09/09 ata6602/ata6603 figure 4-121. programming the fuses waveforms 4.24.7.11 programming the lock bits the algorithm for programming the lock bits is as follows (refer to ?programming the flash? on page 305 for details on command and data loading): 1. a: load command ?0010 0000?. 2. c: load data low byte. bit n = ?0? programs the lock bit. if lb mode 3 is programmed (lb1 and lb2 is programmed), it is not possible to program the boot lock bits by any external programming mode. 3. give wr a negative pulse and wait for rdy/bsy to go high. the lock bits can only be cleared by executing chip erase. 4.24.7.12 reading the fuse and lock bits the algorithm for reading the fuse and lock bits is as follows (refer to ?programming the flash? on page 305 for details on command loading): 1. a: load command ?0000 0100?. 2. set oe to ?0?, bs2 to ?0? and bs1 to ?0?. the status of the fuse low bits can now be read at data (?0? means programmed). 3. set oe to ?0?, bs2 to ?1? and bs1 to ?1?. the status of the fuse high bits can now be read at data (?0? means programmed). 4. set oe to ?0?, bs2 to ?1?, and bs1 to ?0?. the status of the extended fuse bits can now be read at data (?0? means programmed). 5. set oe to ?0?, bs2 to ?0? and bs1 to ?1?. the status of the lock bits can now be read at data (?0? means programmed). 6. set oe to ?1?. rdy/bsy wr oe reset +12v pagel 0x40 data data xx xa1 xa0 bs1 xtal1 ac 0x40 data xx ac write fuse low byte write fuse high byte 0x40 data xx ac write extended fuse byte bs2 311 4921e?auto?09/09 ata6602/ata6603 figure 4-122. mapping between bs1, bs2 and the fuse and lock bits during read 4.24.7.13 reading the signature bytes the algorithm for reading the signatur e bytes is as follows (refer to ?programming the flash? on page 305 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte (0x00 - 0x02). 3. set oe to ?0?, and bs1 to ?0?. the selected signature byte can now be read at data. 4. set oe to ?1?. 4.24.7.14 reading the calibration byte the algorithm for reading the calibration byte is as follows (refer to ?programming the flash? on page 305 for details on command and address loading): 1. a: load command ?0000 1000?. 2. b: load address low byte, 0x00. 3. set oe to ?0?, and bs1 to ?1?. the calibration byte can now be read at data. 4. set oe to ?1?. 4.24.7.15 parallel programming characteristics figure 4-123. parallel programming timing, including some general timing requirements lock bits 0 1 bs2 fuse high byte 0 1 bs1 data fuse low byte 0 1 bs2 extended fuse byte data & contol (data, xa0/1, bs1, bs2) xtal1 t xhxl t wlwh t dvxh t xldx t plwl t wlrh wr rdy/bsy pagel t phpl t plbx t bvph t xlwl t wlbx t bvwl wlrl 312 4921e?auto?09/09 ata6602/ata6603 figure 4-124. parallel programming timing, loading sequence with timing requirements (1) note: 1. the timing requirements shown in figure 4-123 on page 311 (i.e., t dvxh , t xhxl , and t xldx ) also apply to loading operation. figure 4-125. parallel programming timing, reading sequence (within the same page) with timing requirements (1) note: 1. the timing requirements shown in figure 4-123 on page 311 (i.e., t dvxh , t xhxl , and t xldx ) also apply to reading operation. xtal1 pagel t plxh t xlxh t xlph addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) load data (low byte) load data (high byte) load data load address (low byte) xtal1 oe addr0 (low byte) data (low byte) data (high byte) addr1 (low byte) data bs1 xa0 xa1 load address (low byte) read data (low byte) read data (high byte) load address (low byte) t bvdv t oldv t xlol t ohdz 313 4921e?auto?09/09 ata6602/ata6603 notes: 1. t wlrh is valid for the write flash, write eepro m, write fuse bits and write lock bits commands. 2. t wlrh_ce is valid for the chip erase command. 4.24.8 serial downloading both the flash and eeprom memo ry arrays can be programmed using the serial spi bus while reset is pulled to gnd. the serial interface consists of pins sck, mosi (input) and miso (out- put). after reset is set low, the programming enable instruction needs to be executed first before program/erase operations can be executed. note, in table 4-125 on page 304 , the pin mapping for spi programming is listed. not all pa rts use the spi pins dedicated for the internal spi interface. table 4-126. parallel programming characteristics, v cc = 5v 10% symbol parameter min typ max units v pp programming enable voltage 11.5 12.5 v i pp programming enable current 250 a t dvxh data and control valid before xtal1 high 67 ns t xlxh xtal1 low to xtal1 high 200 ns t xhxl xtal1 pulse width high 150 ns t xldx data and control hold after xtal1 low 67 ns t xlwl xtal1 low to wr low 0 ns t xlph xtal1 low to pagel high 0 ns t plxh pagel low to xtal1 high 150 ns t bvph bs1 valid before pagel high 67 ns t phpl pagel pulse width high 150 ns t plbx bs1 hold after pagel low 67 ns t wlbx bs2/1 hold after wr low 67 ns t plwl pagel low to wr low 67 ns t bvwl bs1 valid to wr low 67 ns t wlwh wr pulse width low 150 ns t wlrl wr low to rdy/bsy low 0 1 s t wlrh wr low to rdy/bsy high (1) 3.7 4.5 ms t wlrh_ce wr low to rdy/bsy high for chip erase (2) 7.5 9 ms t xlol xtal1 low to oe low 0 ns t bvdv bs1 valid to data valid 0 250 ns t oldv oe low to data valid 250 ns t ohdz oe high to data tri-stated 250 ns 314 4921e?auto?09/09 ata6602/ata6603 figure 4-126. serial programming and verify (1) notes: 1. if the device is clocked by the internal oscillator, it is no need to connect a clock source to the xtal1 pin. 2. v cc - 0.3v < av cc < v cc + 0.3v, however, av cc should always be within 1.8v - 5.5v when programming the eeprom, an auto-erase cycle is built into the self-timed programming operation (in the serial mode only) and there is no need to first execute the chip erase instruction. the chip erase operation turns the content of every memory location in both the program and eeprom arrays into 0xff. depending on cksel fuses, a valid clock must be present. the minimum low and high periods for the serial clock (sck) input are defined as follows: low: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz high: > 2 cpu clock cycles for f ck < 12 mhz, 3 cpu clock cycles for f ck >= 12 mhz 4.24.8.1 serial programming algorithm when writing serial data to the ata6602/ata6603, data is clocked on the rising edge of sck. when reading data from the at a6602/ata6603, data is clocked on the falling edge of sck. see figure 4-127 on page 316 for timing details. to program and verify the ata6602/ata6603 in the serial programming mode, the following sequence is recommended (see four byte instruction formats in table 4-128 on page 316 ): 1. power-up sequence: apply power between v cc and gnd while reset and sck are set to ?0?. in some sys- tems, the programmer can not guarantee that sck is held low during power-up. in this case, reset must be given a positive pulse of at least two cpu clock cycles duration after sck has been set to ?0?. 2. wait for at least 20 ms and enable serial programming by sending the programming enable serial instruction to pin mosi. vcc +2.7v to 5.5v gnd xtal1 reset sck miso avcc +2.7v to 5.5v (2) mosi 315 4921e?auto?09/09 ata6602/ata6603 3. the serial programming instructions will no t work if the communic ation is out of syn- chronization. when in sync. the second byte (0x53), will echo back when issuing the third byte of the programming enable instruction. whether the echo is correct or not, all four bytes of the instruction must be transmitted. if the 0x53 did not echo back, give reset a positive pulse and issue a new programming enable command. 4. the flash is programmed one page at a time. the memory page is loaded one byte at a time by supplying the 6 lsb of the address and data together with the load program memory page instruction. to ensure correct loading of the page, the data low byte must be loaded before data high byte is applied for a given address. the program memory page is stored by loading the write program memory page instruction with the 8 msb of the address. if polling is not used, the user must wait at least t wd_flash before issuing the next page (see table 4-127 on page 316 ). accessing the serial programming inter- face before the flash write operation completes can result in incorrect programming. 5. the eeprom array is programmed one byte at a time by supplying the address and data together with the appropriate write instruction. an eeprom memory location is first automatically erased before new data is written. if pollin g is not used, the user must wait at least t wd_eeprom before issuing the next byte (see table 4-127 on page 316 ). in a chip erased device, no 0xffs in the data file(s) need to be programmed. 6. any memory location can be verified by using the read instruction which returns the content at the selected address at serial output miso. 7. at the end of the programming session, reset can be set high to commence normal operation. 8. power-off sequence (if needed): set reset to ?1?. tu r n v cc power off. 4.24.8.2 data polling flash when a page is being programmed into the flash, reading an address location within the page being programmed will give the value 0xff. at th e time the device is ready for a new page, the programmed value will read correctly. this is used to determine w hen the next page can be writ- ten. note that the entire page is written simultaneously and any address within the page can be used for polling. data po lling of the flash will not work for the value 0xff, so when programming this value, the user will have to wait for at least t wd_flash before programming the next page. as a chip-erased device contains 0xff in all locations, programming of addresses that are meant to contain 0xff, can be skipped. see table 4-127 on page 316 for t wd_flash value. 4.24.8.3 data polling eeprom when a new byte has been written and is being programmed into eeprom, reading the address location being programmed will give the value 0xff. at the time the device is ready for a new byte, the programmed value will read corr ectly. this is used to determine when the next byte can be written. this will not work for the value 0xff, but th e user should have the following in mind: as a chip-erased device contains 0xff in all locations, progra mming of addresses that are meant to contain 0xff, can be skipped. this does not apply if the eeprom is re-pro- grammed without chip eras ing the device. in this case, data po lling cannot be used for the value 0xff, and the user will have to wait at least t wd_eeprom before programming the next byte. see table 4-127 on page 316 for t wd_eeprom value. 316 4921e?auto?09/09 ata6602/ata6603 figure 4-127. serial programming waveforms table 4-127. minimum wait delay before writing the next flash or eeprom location symbol minimum wait delay t wd_flash 4.5 ms t wd_eeprom 3.6 ms t wd_erase 9.0 ms msb msb lsb lsb serial clock input (sck) serial data input (mosi) (miso) sample serial data output table 4-128. serial programming instruction set instruction instruction format operation byte 1 byte 2 byte 3 byte4 programming enable 1010 1100 0101 0011 xxxx xxxx xxxx xxxx enable serial programming after reset goes low. chip erase 1010 1100 100x xxxx xxxx xxxx xxxx xxxx chip erase eeprom and flash. read program memory 0010 h 000 000 a aaaa bbbb bbbb oooo oooo read h (high or low) data o from program memory at word address a : b . load program memory page 0100 h 000 000x xxxx xx bb bbbb iiii iiii write h (high or low) data i to program memory page at word address b . data low byte must be loaded before data high byte is applied within the same address. write program memory page 0100 1100 000 a aaaa bb xx xxxx xxxx xxxx write program memory page at address a : b . read eeprom memory 1010 0000 000x xx aa bbbb bbbb oooo oooo read data o from eeprom memory at address a : b . write eeprom memory 1100 0000 000x xx aa bbbb bbbb iiii iiii write data i to eeprom memory at address a : b . load eeprom memory page (page access) 1100 0001 0000 0000 0000 00 bb iiii iiii load data i to eeprom memory page buffer. after data is loaded, program eeprom page. write eeprom memory page (page access) 1100 0010 00xx xx aa bbbb bb00 xxxx xxxx write eeprom page at address a : b . read lock bits 0101 1000 0000 0000 xxxx xxxx xx oo oooo read lock bits. ?0? = programmed, ?1? = unprogrammed. see table 4-113 on page 298 for details. 317 4921e?auto?09/09 ata6602/ata6603 note: a = address high bits, b = address low bits, h = 0 - low byte, 1 - high byte, o = data out, i = data in, x = do not care 4.24.8.4 spi serial programming characteristics for characteristics of the spi module see ?spi timing characteristics? on page 324 . write lock bits 1010 1100 111x xxxx xxxx xxxx 11 ii iiii write lock bits. set bits = ?0? to program lock bits. see table 4-113 on page 298 for details. read signature byte 0011 0000 000x xxxx xxxx xx bb oooo oooo read signature byte o at address b . write fuse bits 1010 1100 1010 0000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table xxx on page xxx for details. write fuse high bits 1010 1100 1010 1000 xxxx xxxx iiii iiii set bits = ?0? to program, ?1? to unprogram. see table 4-97 on page 268 for details. write extended fuse bits 1010 1100 1010 0100 xxxx xxxx xxxx xxii set bits = ?0? to program, ?1? to unprogram. see table 4-116 on page 300 for details. read fuse bits 0101 0000 0000 0000 xxxx xxxx oooo oooo read fuse bits. ?0? = programmed, ?1? = unprogrammed. see table xxx on page xxx for details. read fuse high bits 0101 1000 0000 1000 xxxx xxxx oooo oooo read fuse high bits. ?0? = programmed, ?1? = unprogrammed. see table 4-97 on page 268 for details. read extended fuse bits 0101 0000 0000 1000 xxxx xxxx oooo oooo read extended fuse bits. ?0? = programmed, ?1? = unprogrammed. see table 4-116 on page 300 for details. read calibration byte 0011 1000 000x xxxx 0000 0000 oooo oooo read calibration byte poll rdy/bsy 1111 0000 0000 0000 xxxx xxxx xxxx xxx o if o = ?1?, a programming operation is still busy. wait until this bit returns to ?0? before applying another command. table 4-128. serial programming instruction set (continued) instruction instruction format operation byte 1 byte 2 byte 3 byte4 318 4921e?auto?09/09 ata6602/ata6603 4.25 electrical characteristics 4.25.1 absolute maximum ratings* operating temperature, t case (1) ....................-40 c to +125 c *notice: stresses beyond those listed under ?absolute max- imum ratings? may cause permanent damage to the device. this is a stre ss rating only and func- tional operation of the device at these or other con- ditions beyond those indicated in the operational sections of this specification is not implied. expo- sure to absolute maximu m rating conditions for extended periods may affect device reliability. notes: 1. t case means the temperature of the heat slug (back- side). it is mandatory that this backside temperature is 125 c in the application. 2. maximum current per port = 30 ma junction temperature, t j ..............................-40 c to +125 c storage temperature......................................-65c to +150c voltage on any pin except reset with respect to ground ................................ -0.5v to v cc +0.5v voltage on reset with respect to ground ..... -0.5v to +13.0v maximum operating voltage ........ .....................................6.0v dc current per i/o pin ................................................40.0 ma dc current v cc and gnd pins ................................200.0 ma injection current at v cc = 0v ...................................5.0 ma (2) injection current at v cc = 5v ......................................1.0 ma 4.25.2 dc characteristics t case = -40c to +125c, v cc = 2.7v to 5.5v (unless otherwise noted) symbol paramete r condition min. (5) typ. max. (5) units v il input low voltage, except xtal1 and reset pin v cc = 2.7v - 5.5v -0.5 0.3v cc (1) v v il1 input low voltage, xtal1 pin v cc = 2.7v - 5.5v -0.5 0.1v cc (1) v v il2 input low voltage, reset pin v cc = 2.7v - 5.5v -0.5 0.1v cc (1) v v ih input high voltage, except xtal1 and reset pins v cc = 2.7v - 5.5v 0.6v cc (2) v cc + 0.5 v v ih1 input high voltage, xtal1 pin v cc = 2.7v - 5.5v 0.7v cc (2) v cc + 0.5 v v ih2 input high voltage, reset pin v cc = 2.7v - 5.5v 0.9v cc (2) v cc + 0.5 v v ol output low voltage (3) i ol = 20ma, v cc = 5v i ol = 5ma, v cc = 3v 0.8 0.5 v v oh output high voltage (4) i oh = -20ma, v cc = 5v i oh = -10ma, v cc = 3v 4.1 2.3 v i il input leakage current i/o pin v cc = 5.5v, pin low (absolute value) 50 na i ih input leakage current i/o pin v cc = 5.5v, pin high (absolute value) 50 na r rst reset pull-up resistor vcc = 5.0v, vin = 0v 30 60 k r pu i/o pin pull-up resistor 20 50 k 319 4921e?auto?09/09 ata6602/ata6603 notes: 1. ?max? means the highest value where the pin is guaranteed to be read as low 2. ?min? means the lowest value where t he pin is guaranteed to be read as high 3. although each i/o port can sink more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), th e following must be observed: ata6602/ata6603: 1] the sum of all iol, for ports c0 - c5, should not exceed 100 ma. 2] the sum of all iol, for ports c6 , d0 - d4, should not exceed 100 ma. 3] the sum of all iol, for ports b0 - b7, d5 - d7, should not exceed 100 ma. if iol exceeds the test condition, vol may exceed the related sp ecification. pins are not guar anteed to sink current greater than the listed test condition. 4. although each i/o port can source more than the test conditions (20ma at v cc = 5v, 10ma at v cc = 3v) under steady state conditions (non-transient), th e following must be observed: ata6602/ata6603: 1] the sum of all ioh, for ports c0 - c5, should not exceed 100 ma. 2] the sum of all ioh, for ports c6 , d0 - d4, should not exceed 100 ma. 3] the sum of all ioh, for ports b0 - b7, d5 - d7, should not exceed 100 ma. if ioh exceeds the test condition, voh ma y exceed the related specification. pins are not guaranteed to source current greater than the listed test condition. 5. all dc characteristics contained in this datasheet are based on actual ata6602 microcontrollers characterization. 6. values with ?power reduction register - prr? enabled (0xef). i cc power supply current (6) active 4mhz, v cc = 3v (ata6602/ata6603l) 1.8 3.0 ma active 8mhz, v cc = 5v (ata6602/ata6603) 6.0 10 ma active 15mhz, v cc = 5v (ata6602/ata6603) 10.0 16 ma idle 4mhz, v cc = 3v (ata6602/ata6603v) 0.4 1 ma idle 8mhz, v cc = 5v (ata6602/ata6603l) 1.4 2.4 ma idle 15mhz, v cc = 5v (ata6602/ata6603) 2.8 4 ma power-down mode wdt enabled, v cc = 3v 8 30 a wdt enabled, v cc = 5v 12.6 50 a wdt disabled, v cc = 3v 5 24 a wdt disabled, v cc = 5v 6.6 36 a v acio analog comparator input offset voltage v cc = 5v v in = v cc /2 10 40 mv i aclk analog comparator input leakage current v cc = 5v v in = v cc /2 -50 50 na t acid analog comparator propagation delay v cc = 4.5v 140 ns 4.25.2 dc characteristics (continued) t case = -40c to +125c, v cc = 2.7v to 5.5v (unless otherwise noted) symbol paramete r condition min. (5) typ. max. (5) units 320 4921e?auto?09/09 ata6602/ata6603 4.25.3 external clock drive waveforms figure 4-128. external clock drive waveforms 4.25.4 external clock drive 4.25.5 maximum speed versus v cc maximum frequency is dependent on v cc. as shown in figure 4-129 , the maximum frequency vs. v cc curve is linear between 2.7v < v cc < 4.5v. figure 4-129. maximum frequency versus v cc , ata6602/ata6603 v il1 v ih1 t chcx t clch t clcx t clcl t chcx t chcl table 4-129. external clock drive symbol parameter v cc = 2.7v-5.5v v cc = 4.5v-5.5v units min. max. min. max. 1/t clcl oscillator frequency 0 8 0 16 mhz t clcl clock period 125 62.5 ns t chcx high time 50 25 ns t clcx low time 50 25 ns t clch rise time 1.6 0.5 s t chcl fall time 1.6 0.5 s t clcl change in period from one clock cycle to the next 22% 16 mhz 8 mhz 2.7v 4.5v 5.5v safe operating area 321 4921e?auto?09/09 ata6602/ata6603 4.26 lin re-synchronization algorithm 4.26.1 synchronization algorithm the possibility to change the value of osccal during the osc illator operation allows for in-situ calibration of the slave node to entering master frames. the principle of operation is to measure the tbit during the synch byte and to change the calib ration value of osccal to recover from local frequency drifts due to local voltage or temperature deviation. the algorithm used for the synchronization of the internal rc oscillator is depicted in figure 4-130 . figure 4-130. dichotomic algorithm used for lin slave clock re-synchronization 4.26.2 precaution against osccal discontinuity the figure 5-26 on page 338 illustrates the on-purpose discontinuity of rc frequency versus osccal value. for one correct re-synchroniza tion, the frequency change must be kept on the same side of the discontinuity (no change of osccal[7]). sinc e there will be no device having frequency changed by more than 10% (see figure 5-24 on page 337 ), thus no reason to change the frequency value by more than 10%. therefore, when calibration tries to cross the border because of subsequent increase (or decrease) in osccal values, then the routine must be stopped. example: for parts operating in the lower part of the curve, if new_osccal >127 then new_osccal = 127. similar for parts operating on the high side of the discontinuity. measuring actual tbit increment osccal decrement osccal -2% < delta(tbit) < 2% delta(tbit) > 2% delta(tbit) < -2% stop: oscillator calibrated y n n 322 4921e?auto?09/09 ata6602/ata6603 4.26.2.1 rc oscillator precision for lin slave implementation for lin slave devices, the precision of the rc os cillator before a nd after re-synchronization are described in the table 4-130 . 5. 2-wire serial interface characteristics table 5-1 describes the requirements for devices connected to the 2-wire serial bus. the ata6602/ata6603 2-wire serial interface meets or exceeds these requirements under the noted conditions. timing symbols refer to figure 5-1 on page 324 . table 4-130. oscillator tolerance before and a fter re-synchronization algorithm (2.7v < v cc <5.5v, -40 c to +125 c) parameter clock tolerance f/f master f tol_unsynch deviation of slave node clock from the nominal clock rate before synchronization; relevant for nodes making use of synchronization and direct synch break detection. 14.0% f tol_synch deviation of slave node clock relative to the master node clock after synchronization; relevant for nodes making use of synchronization; any slave node must stay within this tolerance for all fields of a frame which follow the synch field. note: for communication between any two nodes their bit rate must not differ by more than 2%. 2.0% table 5-1. 2-wire serial bus requirements symbol parameter condition min max units vil input low-voltage -0.5 0.3 v cc v vih input high-voltage 0.7 v cc v cc + 0.5 v vhys (1) hysteresis of schmitt trigger inputs 0.05 v cc (2) ?v vol (1) output low-voltage 3 ma sink current 0 0.4 v tr (1) rise time for both sda and scl 20 + 0.1c b (2,3) 300 ns tof (1) output fall time from v ihmin to v ilmax 10 pf < c b < 400 pf (3) 20 + 0.1c b (2,3) 250 ns tsp (1) spikes suppressed by input filter 0 50 (2) ns i i input current each i/o pin 0.1v cc < v i < 0.9v cc -10 10 a notes: 1. in ata6602/ata6603, this parameter is characterized and not 100% tested. 2. required only for f scl > 100 khz. 3. c b = capacitance of one bus line in pf. 4. f ck = cpu clock frequency 5. this requirement applies to all ata6602/ata6603 2-wire serial interface operation. other devi ces connected to the 2-wire serial bus need only obey the general f scl requirement. 6. the actual low period generated by the ata6602/ata6603 2-wire serial interface is (1/f scl - 2/f ck ), thus f ck must be greater than 6 mhz for the low time requirement to be strictly met at f scl = 100 khz. 7. the actual low period generated by the ata6602/ata6603 2-wire serial interface is (1/f scl - 2/f ck ), thus the low time requirement will not be strictly met for f scl > 308 khz when f ck = 8 mhz. still, ata6602/ata6603 devices connected to the bus may communicate at full speed (400 khz) with other at a6602/ata6603 devices, as well as any other device with a proper t low acceptance margin. 323 4921e?auto?09/09 ata6602/ata6603 c i (1) capacitance for each i/o pin ? 10 pf f scl scl clock frequency f ck (4) > max(16f scl , 250khz) (5) 0 400 khz rp value of pull-up resistor f scl 100 khz f scl > 100 khz t hd;sta hold time (repeated) start condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t low low period of the scl clock f scl 100 khz (6) 4.7 ? s f scl > 100 khz (7) 1.3 ? s t high high period of the scl clock f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t su;sta set-up time for a repeated start condition f scl 100 khz 4.7 ? s f scl > 100 khz 0.6 ? s t hd;dat data hold time f scl 100 khz 0 3.45 s f scl > 100 khz 0 0.9 s t su;dat data setup time f scl 100 khz 250 ? ns f scl > 100 khz 100 ? ns t su;sto setup time for stop condition f scl 100 khz 4.0 ? s f scl > 100 khz 0.6 ? s t buf bus free time between a stop and start condition f scl 100 khz 4.7 ? s f scl > 100 khz 1.3 ? s table 5-1. 2-wire serial bus requirements (continued) symbol parameter condition min max units notes: 1. in ata6602/ata6603, this parameter is characterized and not 100% tested. 2. required only for f scl > 100 khz. 3. c b = capacitance of one bus line in pf. 4. f ck = cpu clock frequency 5. this requirement applies to all ata6602/ata6603 2-wire serial interface operation. other devi ces connected to the 2-wire serial bus need only obey the general f scl requirement. 6. the actual low period generated by the ata6602/ata6603 2-wire serial interface is (1/f scl - 2/f ck ), thus f ck must be greater than 6 mhz for the low time requirement to be strictly met at f scl = 100 khz. 7. the actual low period generated by the ata6602/ata6603 2-wire serial interface is (1/f scl - 2/f ck ), thus the low time requirement will not be strictly met for f scl > 308 khz when f ck = 8 mhz. still, ata6602/ata6603 devices connected to the bus may communicate at full speed (400 khz) with other at a6602/ata6603 devices, as well as any other device with a proper t low acceptance margin. v cc 0,4v ? 3ma ---------------------------- 1000ns c b ------------------- v cc 0,4v ? 3ma ---------------------------- 300ns c b --------------- - 324 4921e?auto?09/09 ata6602/ata6603 figure 5-1. 2-wire serial bus timing 5.1 spi timing characteristics see figure 5-2 on page 325 and figure 5-3 on page 325 for details. note: 1. in spi programming mode the minimum sck high/low period is: - 2 t clcl for f ck < 12 mhz - 3 t clcl for f ck > 12 mhz t su;sta t low t high t low t of t hd;sta t hd;dat t su;dat t su;sto t buf scl sda t r table 5-2. spi timing parameters description mode min typ max 1 sck period master see table 4-69 on page 188 ns 2 sck high/low master 50% duty cycle 3 rise/fall time master 3.6 4 setup master 10 5 hold master 10 6 out to sck master 0.5 ? t sck 7 sck to out master 10 8 sck to out high master 10 9ss low to out slave 15 10 sck period slave 4 ? t ck 11 sck high/low (1) slave 2 ? t ck 12 rise/fall time slave 1600 13 setup slave 10 14 hold slave t ck 15 sck to out slave 15 16 sck to ss high slave 20 17 ss high to tri-state slave 10 18 ss low to sck slave 20 325 4921e?auto?09/09 ata6602/ata6603 figure 5-2. spi interface timing requirements (master mode) figure 5-3. spi interface timing requirements (slave mode) mo si (data output) sck (cpol = 1) mi so (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 6 1 22 3 4 5 8 7 mi so (data output) sck (cpol = 1) mo si (data input) sck (cpol = 0) ss msb lsb lsb msb ... ... 10 11 11 12 13 14 17 15 9 x 16 326 4921e?auto?09/09 ata6602/ata6603 5.2 adc characteristics table 5-3. adc characteristics symbol parameter condi tion min typ max units resolution 10 bits absolute accu racy (including inl, dnl, quantization error, gain and offset error) v ref = 4v, v cc = 4v, adc clock = 200 khz 23.5lsb v ref = 4v, v cc = 4v, adc clock = 200 khz noise reduction mode 23.5lsb integral non-linearity (inl) v ref = 4v, v cc = 4v, adc clock = 200 khz 0.6 2.5 lsb differential non-linearity (dnl) v ref = 4v, v cc = 4v, adc clock = 200 khz 0.40 1.0 lsb gain error v ref = 4v, v cc = 4v, adc clock = 200 khz -3.5 -1.3 3.5 lsb offset error v ref = 4v, v cc = 4v, adc clock = 200 khz 1.8 3.5 lsb conversion time free running conversion 13 cycles s clock frequency 50 200 khz av cc analog supply voltage v cc - 0.3 v cc + 0.3 v v ref reference voltage 1.0 av cc v v in input voltage gnd v ref v v int internal voltage reference 1.0 1.1 1.2 v r ref reference input resistance 22.4 32 41.6 k r ain analog input resistance 100 m 327 4921e?auto?09/09 ata6602/ata6603 5.3 ata6602/ata6603 typi cal characteristics note: values of temp refer to t case 5.3.1 active supply current figure 5-4. active supply current versus frequency (1 mhz to 20 mhz), temp = 125c figure 5-5. idle supply current versus frequency (1 mhz to 20 mhz), temp = 125c 5.5 v 5.0 v 4.5 v 3.3 v 3.0 v 2.7 v 0 2 4 6 8 10 12 14 16 18 20 0 2 4 6 8 10 12 14 16 18 20 frequency (mhz) i cc (ma) 5.5 v 5.0 v 4.5 v 3.3 v 3.0 v 2.7 v 0 2 4 6 02468101214161820 frequency (mhz) i cc (ma) 328 4921e?auto?09/09 ata6602/ata6603 5.3.1.1 power-down supply current figure 5-6. power-down supply current versus v cc (watchdog timer disabled) figure 5-7. power-down supply current versus v cc (watchdog timer enabled) power-down supply current vs. v cc watchdog timer disabled / vt fast corners excluded 0 1 2 3 4 5 6 7 8 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 125 85 25 -40 power-down supply current vs. v cc watchdog timer disabled / vt fast corners excluded 0 1 2 3 4 5 6 7 8 2.5 3 3.5 4 4.5 5 5.5 v cc (v) i cc (ua) 125 85 25 -40 329 4921e?auto?09/09 ata6602/ata6603 5.3.1.2 pin pull-up figure 5-8. i/o pin pull-up resistor current vs. input voltage (v cc = 5v) figure 5-9. output low voltage vs. output low current (v cc = 5v) 0 20 40 60 80 100 120 140 160 0123456 v op (v) i op (ua) 125 -40 i/o pin pull-up resistor current vs. input voltage v = 5v cc i/o pin output voltage vs. sink current vcc = 5.00v 125 ?c 85 ?c 25 ?c -40 ?c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 2 4 6 8 101214161820 i ol (ma) vol (v) 330 4921e?auto?09/09 ata6602/ata6603 figure 5-10. output low voltage vs. output low current (v cc = 3v) figure 5-11. output high voltage vs . output high current (v cc = 5v) i/o pin output voltage vs. sink current vcc = 3v 125 ?c 85 ?c 25 ?c -40 ?c 0 0.2 0.4 0.6 0.8 1 1.2 0 2 4 6 8 101214161820 vol (v) iol (ma) i/o pin output voltage vs. source current vcc = 5.00v 125 ?c 85 ?c 25 ?c -40 ?c 4 4.2 4.4 4.6 4.8 5 5.2 0 2 4 6 8 10 12 14 16 18 20 i oh (ma) voh (v) 331 4921e?auto?09/09 ata6602/ata6603 figure 5-12. output high voltage vs. output high current (v cc = 3v) figure 5-13. reset pull-up resist or current vs. reset pin voltage (v cc = 5v) i/o pin output voltage vs. source current v cc = 3v 125 ?c 85 ?c 25 ?c -40 ?c 0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 101214161820 i oh (ma) current (v) 0 20 40 60 80 100 120 140 160 0123456 v op (v) i op (ua) 125 -40 i/o pin pull-up resistor current vs. input voltage v = 5v cc 332 4921e?auto?09/09 ata6602/ata6603 5.3.1.3 pin driver strength figure 5-14. output low voltage versus output low current (v cc = 5v) figure 5-15. output low voltage versus output low current (v cc = 3v) i/o pin output voltage vs. sink current vcc = 5.00v 125 ?c 85 ?c 25 ?c -40 ?c 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0 2 4 6 8 101214161820 i ol (ma) vol (v) i/o pin output voltage vs. sink current vcc = 3v 125 ?c 85 ?c 25 ?c -40 ?c 0 0.2 0.4 0.6 0.8 1 1.2 0 2 4 6 8 101214161820 vol (v) iol (ma) 333 4921e?auto?09/09 ata6602/ata6603 figure 5-16. output high voltage versus output high current (v cc = 5v) figure 5-17. output high voltage versus output high current (v cc = 3v) i/o pin output voltage vs. source current vcc = 5.00v 125 ?c 85 ?c 25 ?c -40 ?c 4 4.2 4.4 4.6 4.8 5 5.2 0 2 4 6 8 101214161820 i oh (ma) voh (v) i/o pin output voltage vs. source current v cc = 3v 125 ?c 85 ?c 25 ?c -40 ?c 0 0.5 1 1.5 2 2.5 3 3.5 0 2 4 6 8 101214161820 i oh (ma) current (v) 334 4921e?auto?09/09 ata6602/ata6603 5.3.1.4 pin thresholds and hysteresis figure 5-18. i/o pin input threshold versus v cc (vih, i/o pin read as 1) figure 5-19. i/o pin input threshold versus v cc (vil, i/o pin read as 0) io input threshold voltage vs. v cc v ih, io pin rea d a s '1' 1 1.5 2 2.5 3 3.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) vih (v) 125 85 25 -40 io input threshold voltage vs. v cc v il, io pin rea d a s '0' 125 c -40 c 0 0.5 1 1.5 2 2.5 3 22.533.544.555.56 v cc (v) vil (v) 335 4921e?auto?09/09 ata6602/ata6603 figure 5-20. reset input threshold voltage versus v cc (vih, reset pin read as 1) figure 5-21. reset input threshold voltage versus v cc (vil, reset pin read as 0) reset input threshold voltage vs. v cc v ih, io pin rea d a s '1' 125 ?c 85 ?c 25 ?c -40 ?c 0 0.5 1 1.5 2 2.5 3 3.5 4 22.533.544.555.5 v cc (v) threshold (v) 125 ?c 85 ?c 25 ?c -40 ?c 0 0.5 1 1.5 2 2.5 2 2.5 3 3.5 4 4.5 5 5.5 v cc (v) threshold (v) 336 4921e?auto?09/09 ata6602/ata6603 5.3.1.5 internal oscillator speed figure 5-22. watchdog oscillato r frequency vs. v cc figure 5-23. calibrated 8 mhz rc oscillato r frequency vs. temperature watchdog oscillator frequency vs. operating voltage 125 ?c 85 ?c 25 ?c -40 ?c 110 112 114 116 118 120 122 124 126 128 130 2.533.544.555.5 v cc (v) f rc (khz) calibrated xxxmhz rc oscillator frequency vs. temperature 5.0 v 2.7 v 7.6 7.7 7.8 7.9 8 8.1 8.2 8.3 8.4 -40-30-20-100 102030405060708090100110120 temperature f rc (mhz) 337 4921e?auto?09/09 ata6602/ata6603 figure 5-24. calibrated 8 mhz rc osc illator frequency vs. v cc figure 5-25. calibrated 8 mhz rc osc illator frequency vs. osca l value (for ata6603) calibrated xxxmhz rc oscillator frequency vs. operating voltage 125 ?c 85 ?c 25 ?c -40 ?c 7 7.2 7.4 7.6 7.8 8 8.2 8.4 2.5 3 3.5 4 4.5 5 5.5 v cc (v) f rc (mhz) calibrated 8 mhz rc oscillator frequency vs. osccal value vcc = 3.0v 125 ?c 85 ?c 25 ?c -40 ?c 2 4 6 8 10 12 14 16 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 oscca l ( x1) f rc (mhz) 338 4921e?auto?09/09 ata6602/ata6603 figure 5-26. calibrated 8 mhz rc oscilla tor frequency vs. oscal va lue (for ata6602 only) 5.3.1.6 bod thresholds and analog comparator offset figure 5-27. bod threshold versus temper ature (bodlevel is 4.0v) calibrated 8mhz rc oscillator frequency vs. osccal value 125 ?c 85 ?c 25 ?c -40 ?c 2 4 6 8 10 12 14 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 oscca l (x1) f rc (mhz) rising vcc falling vcc 4 4.1 4.2 4.3 4.4 4.5 4.6 -55 -45 -35 -25 -15 -5 5 15 25 35 45 55 65 75 85 95 105 115 125 temperature (c) threshold (v) 339 4921e?auto?09/09 ata6602/ata6603 figure 5-28. bod threshold versus temper ature (bodlevel is 2.7v) figure 5-29. bandgap voltage versus v cc rising vcc falling vcc 2.4 2.5 2.6 2.7 2.8 2.9 3 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 temperature (c) threshold (v) 125 c 85 c 25 c -40 c 1.075 1.08 1.085 1.09 1.095 1.1 2.5 3 3.5 4 4.5 5 5.5 v cc (v) bandgap voltage (v) 340 4921e?auto?09/09 ata6602/ata6603 5.3.1.7 peripheral units figure 5-30. analog to digital converter gain versus v cc figure 5-31. analog to digital converter offset versus v cc -1.60 -1.40 -1.20 -1.00 -0.80 -0.60 -0.40 -0.20 0.00 -50 0 50 100 150 temperature error (lsb) 4v idle 4v std 0.00 0.50 1.00 1.50 2.00 2.50 -50 0 50 100 150 temperature error (lsb) 4v idle 4v std 341 4921e?auto?09/09 ata6602/ata6603 figure 5-32. analog to digital converter dnl versus v cc figure 5-33. analog to digital converter inl versus v cc 0.00 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 -50 0 50 100 150 temperature error (lsb) 4v idle 4v std 0.00 0.10 0.20 0.30 0.40 0.50 0.60 0.70 -50 0 50 100 150 temperature error (lsb) 4v idle 4v std 342 4921e?auto?09/09 ata6602/ata6603 5.4 register summary address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page (0xff) reserved ? ? ? ? ? ? ? ? (0xfe) reserved ? ? ? ? ? ? ? ? (0xfd) reserved ? ? ? ? ? ? ? ? (0xfc) reserved ? ? ? ? ? ? ? ? (0xfb) reserved ? ? ? ? ? ? ? ? (0xfa) reserved ? ? ? ? ? ? ? ? (0xf9) reserved ? ? ? ? ? ? ? ? (0xf8) reserved ? ? ? ? ? ? ? ? (0xf7) reserved ? ? ? ? ? ? ? ? (0xf6) reserved ? ? ? ? ? ? ? ? (0xf5) reserved ? ? ? ? ? ? ? ? (0xf4) reserved ? ? ? ? ? ? ? ? (0xf3) reserved ? ? ? ? ? ? ? ? (0xf2) reserved ? ? ? ? ? ? ? ? (0xf1) reserved ? ? ? ? ? ? ? ? (0xf0) reserved ? ? ? ? ? ? ? ? (0xef) reserved ? ? ? ? ? ? ? ? (0xee) reserved ? ? ? ? ? ? ? ? (0xed) reserved ? ? ? ? ? ? ? ? (0xec) reserved ? ? ? ? ? ? ? ? (0xeb) reserved ? ? ? ? ? ? ? ? (0xea) reserved ? ? ? ? ? ? ? ? (0xe9) reserved ? ? ? ? ? ? ? ? (0xe8) reserved ? ? ? ? ? ? ? ? (0xe7) reserved ? ? ? ? ? ? ? ? (0xe6) reserved ? ? ? ? ? ? ? ? (0xe5) reserved ? ? ? ? ? ? ? ? (0xe4) reserved ? ? ? ? ? ? ? ? (0xe3) reserved ? ? ? ? ? ? ? ? (0xe2) reserved ? ? ? ? ? ? ? ? (0xe1) reserved ? ? ? ? ? ? ? ? (0xe0) reserved ? ? ? ? ? ? ? ? note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x 00 - 0x1f are directly bit-accessible usi ng the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical on e to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specifie d bit, and can therefore be used on r egisters containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the ata6602/ata6603 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 5. only valid for ata6602/ata6603 343 4921e?auto?09/09 ata6602/ata6603 (0xdf) reserved ? ? ? ? ? ? ? ? (0xde) reserved ? ? ? ? ? ? ? ? (0xdd) reserved ? ? ? ? ? ? ? ? (0xdc) reserved ? ? ? ? ? ? ? ? (0xdb) reserved ? ? ? ? ? ? ? ? (0xda) reserved ? ? ? ? ? ? ? ? (0xd9) reserved ? ? ? ? ? ? ? ? (0xd8) reserved ? ? ? ? ? ? ? ? (0xd7) reserved ? ? ? ? ? ? ? ? (0xd6) reserved ? ? ? ? ? ? ? ? (0xd5) reserved ? ? ? ? ? ? ? ? (0xd4) reserved ? ? ? ? ? ? ? ? (0xd3) reserved ? ? ? ? ? ? ? ? (0xd2) reserved ? ? ? ? ? ? ? ? (0xd1) reserved ? ? ? ? ? ? ? ? (0xd0) reserved ? ? ? ? ? ? ? ? (0xcf) reserved ? ? ? ? ? ? ? ? (0xce) reserved ? ? ? ? ? ? ? ? (0xcd) reserved ? ? ? ? ? ? ? ? (0xcc) reserved ? ? ? ? ? ? ? ? (0xcb) reserved ? ? ? ? ? ? ? ? (0xca) reserved ? ? ? ? ? ? ? ? (0xc9) reserved ? ? ? ? ? ? ? ? (0xc8) reserved ? ? ? ? ? ? ? ? (0xc7) reserved ? ? ? ? ? ? ? ? (0xc6) udr0 usart i/o data register 210 (0xc5) ubrr0h usart baud rate register high 215 (0xc4) ubrr0l usart baud rate register low 215 (0xc3) reserved ? ? ? ? ? ? ? ? (0xc2) ucsr0c umsel01 umsel00 upm01 upm00 usbs0 ucsz01 /udord0 ucsz00 / ucpha0 ucpol0 213/226 (0xc1) ucsr0b rxcie0 txcie0 udrie0 rxen0 txen0 ucsz02 rxb80 txb80 212 (0xc0) ucsr0a rxc0 txc0 udre0 fe0 dor0 upe0 u2x0 mpcm0 211 5.4 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x 00 - 0x1f are directly bit-accessible usi ng the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical on e to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specifie d bit, and can therefore be used on r egisters containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the ata6602/ata6603 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 5. only valid for ata6602/ata6603 344 4921e?auto?09/09 ata6602/ata6603 (0xbf) reserved ? ? ? ? ? ? ? ? (0xbe) reserved ? ? ? ? ? ? ? ? (0xbd) twamr twam6 twam5 twam4 twam3 twam2 twam1 twam0 ? 239 (0xbc) twcr twint twea twsta twsto twwc twen ? twie 236 (0xbb) twdr 2-wire serial interface data register 238 (0xba) twar twa6 twa5 twa4 twa3 twa2 twa1 twa0 twgce 239 (0xb9) twsr tws7 tws6 tws5 tws4 tws3 ? twps1 twps0 238 (0xb8) twbr 2-wire serial interface bit rate register 236 (0xb7) reserved ? ? ? ? ? ? ? (0xb6) assr ? exclk as2 tcn2ub ocr2aub ocr2bub tcr2aub tcr2bub 179 (0xb5) reserved ? ? ? ? ? ? ? ? (0xb4) ocr2b timer/counter2 output compare register b 176 (0xb3) ocr2a timer/counter2 output compare register a 176 (0xb2) tcnt2 timer/counter2 (8-bit) 176 (0xb1) tccr2b foc2a foc2b ? ? wgm22 cs22 cs21 cs20 175 (0xb0) tccr2a com2a1 com2a0 com2b1 com2b0 ? ? wgm21 wgm20 172 (0xaf) reserved ? ? ? ? ? ? ? ? (0xae) reserved ? ? ? ? ? ? ? ? (0xad) reserved ? ? ? ? ? ? ? ? (0xac) reserved ? ? ? ? ? ? ? ? (0xab) reserved ? ? ? ? ? ? ? ? (0xaa) reserved ? ? ? ? ? ? ? ? (0xa9) reserved ? ? ? ? ? ? ? ? (0xa8) reserved ? ? ? ? ? ? ? ? (0xa7) reserved ? ? ? ? ? ? ? ? (0xa6) reserved ? ? ? ? ? ? ? ? (0xa5) reserved ? ? ? ? ? ? ? ? (0xa4) reserved ? ? ? ? ? ? ? ? (0xa3) reserved ? ? ? ? ? ? ? ? (0xa2) reserved ? ? ? ? ? ? ? ? (0xa1) reserved ? ? ? ? ? ? ? ? (0xa0) reserved ? ? ? ? ? ? ? ? (0x9f) reserved ? ? ? ? ? ? ? ? 5.4 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x 00 - 0x1f are directly bit-accessible usi ng the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical on e to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specifie d bit, and can therefore be used on r egisters containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the ata6602/ata6603 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 5. only valid for ata6602/ata6603 345 4921e?auto?09/09 ata6602/ata6603 (0x9e) reserved ? ? ? ? ? ? ? ? (0x9d) reserved ? ? ? ? ? ? ? ? (0x9c) reserved ? ? ? ? ? ? ? ? (0x9b) reserved ? ? ? ? ? ? ? ? (0x9a) reserved ? ? ? ? ? ? ? ? (0x99) reserved ? ? ? ? ? ? ? ? (0x98) reserved ? ? ? ? ? ? ? ? (0x97) reserved ? ? ? ? ? ? ? ? (0x96) reserved ? ? ? ? ? ? ? ? (0x95) reserved ? ? ? ? ? ? ? ? (0x94) reserved ? ? ? ? ? ? ? ? (0x93) reserved ? ? ? ? ? ? ? ? (0x92) reserved ? ? ? ? ? ? ? ? (0x91) reserved ? ? ? ? ? ? ? ? (0x90) reserved ? ? ? ? ? ? ? ? (0x8f) reserved ? ? ? ? ? ? ? ? (0x8e) reserved ? ? ? ? ? ? ? ? (0x8d) reserved ? ? ? ? ? ? ? ? (0x8c) reserved ? ? ? ? ? ? ? ? (0x8b) ocr1bh timer/counter1 - output compare register b high byte 157 (0x8a) ocr1bl timer/counter1 - output compare register b low byte 157 (0x89) ocr1ah timer/counter1 - output compare register a high byte 157 (0x88) ocr1al timer/counter1 - output compare register a low byte 157 (0x87) icr1h timer/counter1 - input capture register high byte 158 (0x86) icr1l timer/counter1 - inpu t capture register low byte 158 (0x85) tcnt1h timer/counter1 - counter register high byte 157 (0x84) tcnt1l timer/counter1 - counter register low byte 157 (0x83) reserved ? ? ? ? ? ? ? ? (0x82) tccr1c foc1a foc1b ? ? ? ? ? ? 156 (0x81) tccr1b icnc1 ices1 ? wgm13 wgm12 cs12 cs11 cs10 155 (0x80) tccr1a com1a1 com1a0 com1b1 com1b0 ? ? wgm11 wgm10 153 (0x7f) didr1 ? ? ? ? ? ? ain1d ain0d 262 (0x7e) didr0 ? ? adc5d adc4d adc3d adc2d adc1d adc0d 279 5.4 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x 00 - 0x1f are directly bit-accessible usi ng the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical on e to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specifie d bit, and can therefore be used on r egisters containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the ata6602/ata6603 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 5. only valid for ata6602/ata6603 346 4921e?auto?09/09 ata6602/ata6603 (0x7d) reserved ? ? ? ? ? ? ? ? (0x7c) admux refs1 refs0 adlar ? mux3 mux2 mux1 mux0 275 (0x7b) adcsrb ?acme ? ? ? adts2 adts1 adts0 279 (0x7a) adcsra aden adsc adate adif adie adps2 adps1 adps0 276 (0x79) adch adc data register high byte 278 (0x78) adcl adc data register low byte 278 (0x77) reserved ? ? ? ? ? ? ? ? (0x76) reserved ? ? ? ? ? ? ? ? (0x75) reserved ? ? ? ? ? ? ? ? (0x74) reserved ? ? ? ? ? ? ? ? (0x73) reserved ? ? ? ? ? ? ? ? (0x72) reserved ? ? ? ? ? ? ? ? (0x71) reserved ? ? ? ? ? ? ? ? (0x70) timsk2 ? ? ? ? ? ocie2b ocie2a toie2 177 (0x6f) timsk1 ? ?icie1 ? ? ocie1b ocie1a toie1 158 (0x6e) timsk0 ? ? ? ? ? ocie0b ocie0a toie0 128 (0x6d) pcmsk2 pcint23 pcint22 pcint21 pcint20 pcint19 pcint18 pcint17 pcint16 110 (0x6c) pcmsk1 ? pcint14 pcint13 pcint12 pcint11 pcint10 pcint9 pcint8 110 (0x6b) pcmsk0 pcint7 pcint6 pcint5 pcint4 pcint3 pcint2 pcint1 pcint0 110 (0x6a) reserved ? ? ? ? ? ? ? ? (0x69) eicra ? ? ? ? isc11 isc10 isc01 isc00 107 (0x68) pcicr ? ? ? ? ? pcie2 pcie1 pcie0 (0x67) reserved ? ? ? ? ? ? ? ? (0x66) osccal oscillator calibration register 56 (0x65) reserved ? ? ? ? ? ? ? ? (0x64) prr prtwi prtim2 prtim0 ? prtim1 prspi prusart0 pradc 64 (0x63) reserved ? ? ? ? ? ? ? ? (0x62) reserved ? ? ? ? ? ? ? ? (0x61) clkpr clkpce ? ? ? clkps3 clkps2 clkps1 clkps0 59 (0x60) wdtcsr wdif wdie wdp3 wdce wde wdp2 wdp1 wdp0 76 5.4 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x 00 - 0x1f are directly bit-accessible usi ng the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical on e to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specifie d bit, and can therefore be used on r egisters containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the ata6602/ata6603 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 5. only valid for ata6602/ata6603 347 4921e?auto?09/09 ata6602/ata6603 0x3f (0x5f) sreg i t h s v n z c 33 0x3e (0x5e) sph ? ? ? ? ? (sp10) 5. sp9 sp8 35 0x3d (0x5d) spl sp7 sp6 sp5 sp4 sp3 sp2 sp1 sp0 35 0x3c (0x5c) reserved ? ? ? ? ? ? ? ? 0x3b (0x5b) reserved ? ? ? ? ? ? ? ? 0x3a (0x5a) reserved ? ? ? ? ? ? ? ? 0x39 (0x59) reserved ? ? ? ? ? ? ? ? 0x38 (0x58) reserved ? ? ? ? ? ? ? ? 0x37 (0x57) spmcsr spmie (rwwsb) 5. ?(rwwsre) 5. blbset pgwrt pgers selfprgen 287 0x36 (0x56) reserved ? ? ? ? ? ? ? ? 0x35 (0x55) mcucr ? ? ?pud ? ? ivsel ivce 0x34 (0x54) mcusr ? ? ? ? wdrf borf extrf porf 0x33 (0x53) smcr ? ? ? ? sm2 sm1 sm0 se 61 0x32 (0x52) reserved ? ? ? ? ? ? ? ? 0x31 (0x51) reserved ? ? ? ? ? ? ? ? 0x30 (0x50) acsr acd acbg aco aci acie acic acis1 acis0 261 0x2f (0x4f) reserved ? ? ? ? ? ? ? ? 0x2e (0x4e) spdr spi data register 189 0x2d (0x4d) spsr spif wcol ? ? ? ? ? spi2x 189 0x2c (0x4c) spcr spie spe dord mstr cpol cpha spr1 spr0 187 0x2b (0x4b) gpior2 general purpose i/o register 2 48 0x2a (0x4a) gpior1 general purpose i/o register 1 48 0x29 (0x49) reserved ? ? ? ? ? ? ? ? 0x28 (0x48) ocr0b timer/counter0 output compare register b 0x27 (0x47) ocr0a timer/counter0 output compare register a 0x26 (0x46) tcnt0 timer/counter0 (8-bit) 0x25 (0x45) tccr0b foc0a foc0b ? ? wgm02 cs02 cs01 cs00 0x24 (0x44) tccr0a com0a1 com0a0 com0b1 com0b0 ? ?wgm01wgm00 0x23 (0x43) gtccr tsm ? ? ? ? ? psrasy psrsync 131/181 0x22 (0x42) eearh (eeprom address register high byte) 5. 43 0x21 (0x41) eearl eeprom address register low byte 43 0x20 (0x40) eedr eeprom data register 43 5.4 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x 00 - 0x1f are directly bit-accessible usi ng the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical on e to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specifie d bit, and can therefore be used on r egisters containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the ata6602/ata6603 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 5. only valid for ata6602/ata6603 348 4921e?auto?09/09 ata6602/ata6603 0x1f (0x3f) eecr ? ? eepm1 eepm0 eerie eempe eepe eere 43 0x1e (0x3e) gpior0 general purpose i/o register 0 48 0x1d (0x3d) eimsk ? ? ? ? ? ? int1 int0 108 0x1c (0x3c) eifr ? ? ? ? ? ? intf1 intf0 108 0x1b (0x3b) pcifr ? ? ? ? ? pcif2 pcif1 pcif0 0x1a (0x3a) reserved ? ? ? ? ? ? ? ? 0x19 (0x39) reserved ? ? ? ? ? ? ? ? 0x18 (0x38) reserved ? ? ? ? ? ? ? ? 0x17 (0x37) tifr2 ? ? ? ? ? ocf2b ocf2a tov2 177 0x16 (0x36) tifr1 ? ?icf1 ? ? ocf1b ocf1a tov1 159 0x15 (0x35) tifr0 ? ? ? ? ?ocf0bocf0atov0 0x14 (0x34) reserved ? ? ? ? ? ? ? ? 0x13 (0x33) reserved ? ? ? ? ? ? ? ? 0x12 (0x32) reserved ? ? ? ? ? ? ? ? 0x11 (0x31) reserved ? ? ? ? ? ? ? ? 0x10 (0x30) reserved ? ? ? ? ? ? ? ? 0x0f (0x2f) reserved ? ? ? ? ? ? ? ? 0x0e (0x2e) reserved ? ? ? ? ? ? ? ? 0x0d (0x2d) reserved ? ? ? ? ? ? ? ? 0x0c (0x2c) reserved ? ? ? ? ? ? ? ? 0x0b (0x2b) portd portd7 portd6 portd5 portd4 portd3 portd2 portd1 portd0 105 0x0a (0x2a) ddrd ddd7 ddd6 ddd5 ddd4 ddd3 ddd2 ddd1 ddd0 106 0x09 (0x29) pind pind7 pind6 pind5 pind4 pind3 pind2 pind1 pind0 106 0x08 (0x28) portc ? portc6 portc5 portc4 portc3 portc2 portc1 portc0 105 0x07 (0x27) ddrc ? ddc6 ddc5 ddc4 ddc3 ddc2 ddc1 ddc0 105 0x06 (0x26) pinc ? pinc6 pinc5 pinc4 pinc3 pinc2 pinc1 pinc0 105 0x05 (0x25) portb portb7 portb6 portb5 portb4 portb3 portb2 portb1 portb0 105 0x04 (0x24) ddrb ddb7 ddb6 ddb5 ddb4 ddb3 ddb2 ddb1 ddb0 105 0x03 (0x23) pinb pinb7 pinb6 pinb5 pinb4 pinb3 pinb2 pinb1 pinb0 105 0x02 (0x22) reserved ? ? ? ? ? ? ? ? 0x01 (0x21) reserved ? ? ? ? ? ? ? ? 0x0 (0x20) reserved ? ? ? ? ? ? ? ? 5.4 register summary (continued) address name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 page note: 1. for compatibility with future devices, reserved bits shou ld be written to zero if accessed. reserved i/o memory addresse s should never be written. 2. i/o registers within the address range 0x 00 - 0x1f are directly bit-accessible usi ng the sbi and cbi instructions. in these registers, the value of single bits can be ch ecked by using the sbis and sbic instructions. 3. some of the status flags are cleared by writing a logical on e to them. note that, unlike most other avrs, the cbi and sbi instructions will only operate on the specifie d bit, and can therefore be used on r egisters containing such status flags. the cbi and sbi instructions work with registers 0x00 to 0x1f only. 4. when using the i/o specific commands in and out, the i/o addresses 0x00 - 0x3f must be used. when addressing i/o registers as data space using ld and st instructions, 0x20 must be added to these addresses. the ata6602/ata6603 is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in opcode for the in and out instructions. for the extended i/o space from 0x60 - 0xff in sram, only the st/sts/std and ld/lds/ldd instructions can be used. 5. only valid for ata6602/ata6603 349 4921e?auto?09/09 ata6602/ata6603 5.5 instruction set summary mnemonics operands description operation flags #clocks arithmetic and logic instructions add rd, rr add two registers rd rd + rr z,c,n,v,h 1 adc rd, rr add with carry two registers rd rd + rr + c z,c,n,v,h 1 adiw rdl,k add immediate to word rdh:rdl rdh:rdl + k z,c,n,v,s 2 sub rd, rr subtract two registers rd rd - rr z,c,n,v,h 1 subi rd, k subtract constant from register rd rd - k z,c,n,v,h 1 sbc rd, rr subtract with carry two registers rd rd - rr - c z,c,n,v,h 1 sbci rd, k subtract with carry constant from reg. rd rd - k - c z,c,n,v,h 1 sbiw rdl,k subtract immediate from word rdh:rdl rdh:rdl - k z,c,n,v,s 2 and rd, rr logical and registers rd rd ? rr z,n,v 1 andi rd, k logical and register and constant rd rd ? k z,n,v 1 or rd, rr logical or registers rd rd v rr z,n,v 1 ori rd, k logical or register and constant rd rd v k z,n,v 1 eor rd, rr exclusiv e or registers rd rd rr z,n,v 1 com rd one?s complement rd 0xff ? rd z,c,n,v 1 neg rd two?s complement rd 0x00 ? rd z,c,n,v,h 1 sbr rd,k set bit(s) in register rd rd v k z,n,v 1 cbr rd,k clear bit(s) in register rd rd ? (0xff - k) z,n,v 1 inc rd increment rd rd + 1 z,n,v 1 dec rd decrement rd rd ? 1 z,n,v 1 tst rd test for zero or minus rd rd ? rd z,n,v 1 clr rd clear register rd rd rd z,n,v 1 ser rd set register rd 0xff none 1 mul rd, rr multiply unsigned r1:r0 rd x rr z,c 2 muls rd, rr multiply signed r1:r0 rd x rr z,c 2 mulsu rd, rr multiply signed with unsigned r1:r0 rd x rr z,c 2 fmul rd, rr fractional multiply unsigned r1:r0 (rd x rr) << 1 z,c 2 fmuls rd, rr fractional multiply signed r1:r0 (rd x rr) << 1 z,c 2 fmulsu rd, rr fractional multiply signed with unsigned r1:r0 (rd x rr) << 1 z,c 2 branch instructions rjmp k relative jump pc pc + k + 1 none 2 ijmp indirect jump to (z) pc z none 2 jmp (1) kdirect jump pc k none 3 rcall k relative subroutine call pc pc + k + 1 none 3 icall indirect call to (z) pc z none 3 call (1) k direct subroutine call pc k none 4 ret subroutine return pc stack none 4 reti interrupt return pc stack i 4 cpse rd,rr compare, skip if equal if (rd = rr) pc pc + 2 or 3 none 1/2/3 cp rd,rr compare rd ? rr z, n,v,c,h 1 cpc rd,rr compare with carry rd ? rr ? c z, n,v,c,h 1 cpi rd,k compare register with immediate rd ? k z, n,v,c,h 1 sbrc rr, b skip if bit in register cleared if (rr(b)=0) pc pc + 2 or 3 none 1/2/3 note: 1. these instructions are only available in ata6603 350 4921e?auto?09/09 ata6602/ata6603 sbrs rr, b skip if bit in register is set if (rr(b)=1) pc pc + 2 or 3 none 1/2/3 sbic p, b skip if bit in i/o register cleared if (p(b)=0) pc pc + 2 or 3 none 1/2/3 sbis p, b skip if bit in i/o register is set if (p(b)=1) pc pc + 2 or 3 none 1/2/3 brbs s, k branch if status flag set if (sreg(s) = 1) then pc pc+k + 1 none 1/2 brbc s, k branch if status flag cleared if (sreg(s) = 0) then pc pc+k + 1 none 1/2 breq k branch if equal if (z = 1) then pc pc + k + 1 none 1/2 brne k branch if not equal if (z = 0) then pc pc + k + 1 none 1/2 brcs k branch if carry set if (c = 1) then pc pc + k + 1 none 1/2 brcc k branch if carry cleared if (c = 0) then pc pc + k + 1 none 1/2 brsh k branch if same or higher if (c = 0) then pc pc + k + 1 none 1/2 brlo k branch if lower if (c = 1) then pc pc + k + 1 none 1/2 brmi k branch if minus if (n = 1) then pc pc + k + 1 none 1/2 brpl k branch if plus if (n = 0) then pc pc + k + 1 none 1/2 brge k branch if greater or equal, signed if (n v= 0) then pc pc + k + 1 none 1/2 brlt k branch if less than zero, signed if (n v= 1) then pc pc + k + 1 none 1/2 brhs k branch if half carry flag set if (h = 1) then pc pc + k + 1 none 1/2 brhc k branch if half carry flag cleared if (h = 0) then pc pc + k + 1 none 1/2 brts k branch if t flag set if (t = 1) then pc pc + k + 1 none 1/2 brtc k branch if t flag cleared if (t = 0) then pc pc + k + 1 none 1/2 brvs k branch if overflow flag is set if (v = 1) then pc pc + k + 1 none 1/2 brvc k branch if overflow flag is cleared if (v = 0) then pc pc + k + 1 none 1/2 brie k branch if interrupt enabled if ( i = 1) then pc pc + k + 1 none 1/2 brid k branch if interrupt disabled if ( i = 0) then pc pc + k + 1 none 1/2 bit and bit-test instructions sbi p,b set bit in i/o register i/o(p,b) 1 none 2 cbi p,b clear bit in i/o register i/o(p,b) 0 none 2 lsl rd logical shift left rd(n+1) rd(n), rd(0) 0 z,c,n,v 1 lsr rd logical shift right rd(n) rd(n+1), rd(7) 0 z,c,n,v 1 rol rd rotate left through carry rd(0) c,rd(n+1) rd(n),c rd(7) z,c,n,v 1 ror rd rotate right through carry rd(7) c,rd(n) rd(n+1),c rd(0) z,c,n,v 1 asr rd arithmetic shift right rd(n) rd(n+1), n=0..6 z,c,n,v 1 swap rd swap nibbles rd(3..0) rd(7..4),rd(7..4) rd(3..0) none 1 bset s flag set sreg(s) 1sreg(s)1 bclr s flag clear sreg(s) 0 sreg(s) 1 bst rr, b bit store from register to t t rr(b) t 1 bld rd, b bit load from t to register rd(b) t none 1 sec set carry c 1c1 clc clear carry c 0 c 1 sen set negative flag n 1n1 cln clear negative flag n 0 n 1 sez set zero flag z 1z1 clz clear zero flag z 0 z 1 sei global interrupt enable i 1i1 5.5 instruction set summary (continued) mnemonics operands description operation flags #clocks note: 1. these instructions are only available in ata6603 351 4921e?auto?09/09 ata6602/ata6603 cli global interrupt disable i 0 i 1 ses set signed test flag s 1s1 cls clear signed test flag s 0 s 1 sev set twos complement overflow. v 1v1 clv clear twos complement overflow v 0 v 1 set set t in sreg t 1t1 clt clear t in sreg t 0 t 1 seh set half carry flag in sreg h 1h1 clh clear half carry flag in sreg h 0 h 1 data transfer instructions mov rd, rr move between registers rd rr none 1 movw rd, rr copy register word rd+1:rd rr+1:rr none 1 ldi rd, k load immediate rd k none 1 ld rd, x load indirect rd (x) none 2 ld rd, x+ load indirect and post-inc. rd (x), x x + 1 none 2 ld rd, - x load indirect and pre-dec. x x - 1, rd (x) none 2 ld rd, y load indirect rd (y) none 2 ld rd, y+ load indirect and post-inc. rd (y), y y + 1 none 2 ld rd, - y load indirect and pre-dec. y y - 1, rd (y) none 2 ldd rd,y+q load indirect with displacement rd (y + q) none 2 ld rd, z load indirect rd (z) none 2 ld rd, z+ load indirect and post-inc. rd (z), z z+1 none 2 ld rd, -z load indirect and pre-dec. z z - 1, rd (z) none 2 ldd rd, z+q load indirect with displacement rd (z + q) none 2 lds rd, k load direct from sram rd (k) none 2 st x, rr store indirect (x) rr none 2 st x+, rr store indirect and post-inc. (x) rr, x x + 1 none 2 st - x, rr store indirect and pre-dec. x x - 1, (x) rr none 2 st y, rr store indirect (y) rr none 2 st y+, rr store indirect and post-inc. (y) rr, y y + 1 none 2 st - y, rr store indirect and pre-dec. y y - 1, (y) rr none 2 std y+q,rr store indirect with displacement (y + q) rr none 2 st z, rr store indirect (z) rr none 2 st z+, rr store indirect and post-inc. (z) rr, z z + 1 none 2 st -z, rr store indirect and pre-dec. z z - 1, (z) rr none 2 std z+q,rr store indirect with displacement (z + q) rr none 2 sts k, rr store direct to sram (k) rr none 2 lpm load program memory r0 (z) none 3 lpm rd, z load program memory rd (z) none 3 lpm rd, z+ load program memory and post-inc rd (z), z z+1 none 3 spm store program memory (z) r1:r0 none - in rd, p in port rd p none 1 out p, rr out port p rr none 1 5.5 instruction set summary (continued) mnemonics operands description operation flags #clocks note: 1. these instructions are only available in ata6603 352 4921e?auto?09/09 ata6602/ata6603 push rr push register on stack stack rr none 2 pop rd pop register from stack rd stack none 2 mcu control instructions nop no operation none 1 sleep sleep (see specific descr. for sleep function) none 1 wdr watchdog reset (see specific descr. for wdr/timer) none 1 break break for on-chip debug only none n/a 5.5 instruction set summary (continued) mnemonics operands description operation flags #clocks note: 1. these instructions are only available in ata6603 353 4921e?auto?09/09 ata6602/ata6603 6. application 6.1 application for low and moderate vcc current demands figure 6-1. typical application circuit note: all open pins are mcm-ios that can be us ed for application-specific purposes. the shown connections between the lin-system-basis-chips a nd the mcm requir e the software in the mcm being programmed correspondingly. ata6602 /ata6603 100n xtal 22p 22p 51k 220p 100n 10 10 100n 100n 1k 100n 22 vs lin gnd 33k 10k wake 1 48 *) *) lin-master pullup 354 4921e?auto?09/09 ata6602/ata6603 6.2 application with extern al npn transistor for i ncreased vcc cu rrent demand figure 6-2. application circuit for increased 5v load demands the vcc pin drives the base of an external npn transistor. the voltage regulation is done via the control loop over the sense input pvcc. note that no current limitation is available in the configuration shown above. note: all open pins are mcm-ios that can be us ed for application-specific purposes. the shown connections between the lin-system-basis-chips a nd the mcm requir e the software in the mcm being programmed correspondingly. ata6602 /ata6603 100n xtal 22p 22p 51k 220p 100n 10 10 100n 100n 1k 100n 22 vs lin gnd 33k 10k wake 1 48 *) *) lin-master pullup 3 2.2 355 4921e?auto?09/09 ata6602/ata6603 8. package information 7. ordering information extended type number program memory package ata6602p-plqw 8 kb flash qfn48, 7 7 ata6603p-plqw 16 kb flash qfn48, 7 7 0.4 0.1 7 5.8 5.5 0.5 nom. 48 12 1 48 37 13 24 25 36 12 1 specifications according to din technical drawings issue: 1; 22.01.03 drawing-no.: 6.543-5089.03-4 package: qfn 48 - 7 x 7 exposed pad 5.8 x 5.8 dimensions in mm not indicated tolerances 0.05 0.23 0.05 -0.05 1 max. +0 356 4921e?auto?09/09 ata6602/ata6603 9. errata 9.1 ata6602, ata6602n, ata6602p ? interrupts may be lost when writing the timer registers in th e asynchronous timer ? flash security 1. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchroniz ed to the asynchronous timer2 clock is written in the cycle before an overflow interrupt occurs, the interrupt may be lost. problem fix/workaround always check that the timer2 timer/counter register, tcnt2, does not have the value 0xff before writing the ti mer2 control register, tccr2, or output compare register, ocr2. 2. flash security problem fix/workaround improved security functions in flash memory. 9.2 ata6603, ata6603n, ata6603p ? interrupts may be lost when writing the timer registers in th e asynchronous timer ? flash security 1. interrupts may be lost when writing the timer registers in the asynchronous timer if one of the timer registers which is synchroniz ed to the asynchronous timer2 clock is written in the cycle before an overflow interrupt occurs, the interrupt may be lost. problem fix/workaround always check that the timer2 timer/counter register, tcnt2, does not have the value 0xff before writing the ti mer2 control register, tccr2, or output compare register, ocr2. 2. flash security problem fix/workaround improved security functions in flash memory. 357 4921e?auto?09/09 ata6602/ata6603 10. revision history please note that the following page numbers referred to in this section refer to the specific revision mentioned, not to this document. revision no. history 4921e-auto-09/09 ? page 6: heading 3.3.1 suppl y pin (vs): text changed ? page 20: el.char. table, row 1.7: text changed 4921d-auto-08/07 ? put datasheet in a new template ? capital t for time generally changed in a lower case t ? all pages: typing modified: sleep mode, silent mode, normal mode, pre-normal mode, unpowered mode ? page 6: section 3.3.3 ?undervo ltage reset output (nres)? added ? page 7: heading 3.3.7 changed in ?input/output pin (txd)? ? page 7: section 3.3.8 ?txd dominant time-out function? changed ? page 7: section 3.3.13 ?tm input pin? trademark added ? page 10: section 3.3.14.3 ?sleep mode? changed ? page 12: section 3.3.14.4: ?pre-normal mode? changed ? page 12: table 3.1: ?table of modes? changed ? page 13: section 3.3.15.1: ?remote wake-up via dominant bus state? changed ? page 13: section 3.3.15.1: ?local wake-up via pin wake? text changed ? page 14: figure 3.7: added ? page 15: section 3.3.16 ?fail-safe features? changed ? page 15: section 3.3.17 ?voltage regulator? changed ? page 16: section 3.3.18 ?watchdog? changed ? page 16: figure 3.9: text changed ? page 19: section 3.4 ?absolute maximum ratings? changed ? page 21: section 3.5 ?electrical charac teristics? numbers 5.2 and 6.8 changed ? page 68: section 4.8.3? power-on reset? some changes ? page 355: ordering information changed ? page 356: errata section added 4921c-auto-12/06 ? put datasheet in a new template ? section 3.3.1 ?supply pin (vs)? on page 6 changed ? section 3.3.7 ?txd dominant time-out function? on page 7 changed ? section 3.3.13.3 ?sleep mode? on page 10 changed ? section 3.3.14 in ?wake-up scenarios from silent or sleep mode? renamed ? section 3.3.15 ?fail-safe features? on page 13 changed ? section 3.3.18 ?temperature monitor at pin temp? on page 17 changed ? table ?electrical characteristics? numbers 10.4, 13.2 and 15.3 on pages 22 to 23 changed ? table ?electrical characteristics? numbers 17.1, 17.2 and 17.3 on page 24 added ? section 4.25.1 ?absolute maximum ratings? on page 317 changed 358 4921e?auto?09/09 ata6602/ata6603 11. table of contents general features........... ................. ................ ................. .............. ............ 1 1 description ............ .............. .............. ............... .............. .............. ............ 1 2 pin configuration ..... ................ ................ ................. ................ ............... 2 3 lin system-basis-chip block .............. .............. .............. .............. .......... 4 3.1 features ...............................................................................................................4 3.2 description ...........................................................................................................4 3.3 functional description ..........................................................................................6 3.4 absolute maximum ratings ...............................................................................19 3.5 electrical characteristics ....................................................................................20 4 microcontroller block ............ .............. .............. .............. .............. ........ 26 4.1 features .............................................................................................................26 4.2 overview ............................................................................................................27 4.3 about code examples .......................................................................................31 4.4 avr cpu core ..................................................................................................31 4.5 avr ata6602/ata6603 memories ...................................................................39 4.6 system clock and clock options .......................................................................49 4.7 power management and sleep modes .............................................................60 4.8 system control and reset .................................................................................66 4.9 interrupts ............................................................................................................77 4.10 i/o-ports .............................................................................................................86 4.11 external interrupts ............................................................................................106 4.12 8-bit timer/counter0 with pwm .......................................................................111 4.13 timer/counter0 and timer/counter1 prescalers .............................................129 4.14 16-bit timer/counter1 with pwm .....................................................................131 4.15 8-bit timer/counter2 with pwm and asynchronous operation .......................160 4.16 serial peripheral interface ? spi ......................................................................182 4.17 usart0 ...........................................................................................................191 4.18 usart in spi mode ........................................................................................218 4.19 2-wire serial interface ......................................................................................228 4.20 analog comparator ..........................................................................................260 4.21 analog-to-digital converter ..............................................................................263 4.22 debugwire on-chip debug system ................................................................280 359 4921e?auto?09/09 ata6602/ata6603 4.23 boot loader support ? read-while-write self-programming, ata6602 and ata6603 .................................................................................282 4.24 memory programming ......................................................................................298 4.25 electrical characteristics ..................................................................................318 4.26 lin re-synchronization algorithm ....................................................................321 5 2-wire serial interface characteristics .. ................ ................ ............. 322 5.1 spi timing characteristics ...............................................................................324 5.2 adc characteristics .........................................................................................326 5.3 ata6602/ata6603 typical characteristics .....................................................327 5.4 register summary ...........................................................................................342 5.5 instruction set summary ..................................................................................349 6 application ............ ................. ................ ................. ................ ............. 353 6.1 application for low and moderate vcc current demands ..............................353 6.2 application with external npn transistor for increased vcc current demand ....................................................................................354 7 ordering information .......... .............. ............... .............. .............. ........ 355 8 package information .............. ................ ................. ................ ............. 355 9 errata ............. ................ ................. ................ .............. .............. ........... 356 9.1 ata6602, ata6602n, ata6602p ..................................................................356 9.2 ata6603, ata6603n, ata6603p ..................................................................356 10 revision history ....... ................ ................ ................. ................ ........... 357 11 table of contents ....... ................ ................. ................ .............. ........... 358 4921e?auto?09/09 headquarters international atmel corporation 2325 orchard parkway san jose, ca 95131 usa tel: 1(408) 441-0311 fax: 1(408) 487-2600 atmel asia unit 1-5 & 16, 19/f bea tower, millennium city 5 418 kwun tong road kwun tong, kowloon hong kong tel: (852) 2245-6100 fax: (852) 2722-1369 atmel europe le krebs 8, rue jean-pierre timbaud bp 309 78054 saint-quentin-en-yvelines cedex france tel: (33) 1-30-60-70-00 fax: (33) 1-30-60-71-11 atmel japan 9f, tonetsu shinkawa bldg. 1-24-8 shinkawa chuo-ku, tokyo 104-0033 japan tel: (81) 3-3523-3551 fax: (81) 3-3523-7581 product contact web site www.atmel.com technical support auto_control@atmel.com sales contact www.atmel.com/contacts literature requests www.atmel.com/literature disclaimer: the information in this document is provided in connection with atmel products. no license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of atmel products. except as set forth in atmel?s terms and condi- tions of sale located on atmel?s web site, atmel assumes no li ability whatsoever and disclaims any express, implied or statutor y warranty relating to its products including, but not limited to, the implied warranty of merchantability, fitness for a particu lar purpose, or non-infringement. in no event shall atmel be liable for any direct, indirect, consequential, punitive, special or i nciden- tal damages (including, without limitation, damages for loss of profits, business interruption, or loss of information) arising out of the use or inability to use this document, even if atme l has been advised of the possibility of such damages. atmel makes no representations or warranties with respect to the accuracy or comp leteness of the contents of this document and reserves the rig ht to make changes to specifications and product descriptions at any time without notice. atmel does not make any commitment to update the information contained her ein. unless specifically provided otherwise, atmel products are not suitable for, and shall not be used in, automotive applications. atmel?s products are not int ended, authorized, or warranted for use as components in applications in tended to support or sustain life. ? 2009 atmel corporation. all rights reserved. atmel ? , logo and combinations thereof, and others are registered trademarks or trademarks of atmel corporation or its subsidiaries. other terms and product names may be trademarks of others. |
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